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13 часов назад

Semiconductor Test Engineer (AI)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Semiconductor Test Engineer (AI) (ATE/DFT): Developing and deploying manufacturing test solutions for next-generation AI accelerator devices across first-silicon bring-up and high-volume production with an accent on ATE test content, high-speed interface testing, and advanced CMOS manufacturing. Focus on debugging silicon failures, optimizing yield, test coverage, test time, and cost, and supporting advanced packaging and die-to-die interconnect test flows.

Location: Bristol, United Kingdom

Company

hirify.global is developing specialized chips and systems to accelerate inference for frontier AI models.

What you will do

  • Develop and maintain ATE test programs for AI accelerator chips through high-volume manufacturing.
  • Implement structural and functional manufacturing tests for advanced CMOS designs, including scan/ATPG, LBIST, MBIST, JTAG, SRAM, DRAM, and high-speed I/O.
  • Bring up first silicon on ATE through pattern debugging, tester correlation, shmooing, and corner analysis.
  • Test high-speed interfaces such as PCIe Gen6 and multi-GHz LPDDR, including at-speed testing and margining.
  • Perform silicon characterization and failure analysis to identify yield limiters and defect mechanisms.
  • Optimize test coverage, test time, cost, and manufacturing robustness while collaborating with design, DFT, packaging, OSAT, and manufacturing partners.

Requirements

  • 5+ years of hands-on semiconductor test engineering experience.
  • Strong experience developing ATE test programs using Advantest 93K, Teradyne, or an equivalent platform.
  • Solid knowledge of DFT methodologies, including scan, ATPG, MBIST, and LBIST, as well as memory test techniques.
  • Experience debugging silicon issues at the tester and correlating failures with design or process causes.
  • Familiarity with advanced CMOS nodes and production test challenges.
  • Ability to work effectively in a cross-functional engineering environment.

Nice to have

  • Experience testing AI accelerators, GPUs, networking ASICs, or other high-performance compute ICs.
  • Experience with PCIe Gen5/Gen6, LPDDR4/5/6, or other high-speed interfaces.
  • Exposure to advanced packaging, chiplets, or multi-die test flows.
  • Experience improving yield, reducing test time, or optimizing cost in high-volume manufacturing.

Culture & Benefits

  • High ownership and autonomy in driving work from concept to hardware.
  • Rapid iteration and direct collaboration with leadership.
  • Close cooperation across hardware, software, silicon, and modelling teams.
  • Inclusive and diverse office environment.
  • Private medical, dental and vision coverage, contributory pension, 25 days of holiday plus bank holidays, and life and critical illness insurance.
  • Meaningful equity participation.

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