Staff BIOS/Platform System Engineer (BIOS/UEFI)

Location: San Jose, California, United States

Salary: $140,000–$220,000 base salary per year, varying by market location, experience, skills, education, and other job-related factors.

Company

hirify.global develops integrated power semiconductors and power delivery systems for customers worldwide.

What you will do

• Lead BIOS-level bring-up and validation for new hardware platforms, including CPU, chipset, and DDR5/DDR6 memory subsystems.
• Develop and execute validation plans for BIOS features, boot flows, ACPI and power management, and platform security features.
• Analyze and customize BIOS/UEFI firmware for AMD EPYC/Ryzen, Intel Core/Xeon, and ARM-based platforms.
• Configure and validate DDR5 memory, including SPD/XMP programming, memory training, RAS features, and JEDEC compliance.
• Resolve hardware-firmware interface issues such as POST failures, memory training errors, PCIe enumeration problems, and thermal or power sequencing anomalies.
• Support manufacturing and sustaining engineering, collaborate with CPU vendors, and maintain validation reports, issue logs, debug guides, and technical documentation.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• At least 3 years of hands-on BIOS/UEFI firmware development or validation experience.
• Experience with at least two of AMD, Intel, or ARM CPU architectures and their relevant firmware frameworks.
• Strong knowledge of DDR5 architecture, training algorithms, SPD/MR registers, RAS features, and platform interfaces including PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.
• Proficiency in C/C++, Python, Bash, UEFI/EDK2, SMM, DXE, PEI, and ACPI/ASL.
• Experience with JTAG debuggers, protocol analyzers, oscilloscopes, serial consoles, schematics, datasheets, and silicon vendor documentation.

Nice to have

• Experience with AMD PSP, Intel ME/CSME, ARM TrustZone, OpenBMC, IPMI, or Redfish.
• Knowledge of server RAS features such as DRAM ECC, memory mirroring, patrol scrub, and MCA.
• Experience with PCIe Gen 5, CXL 2.0/3.0, JEDEC DDR5 compliance testing, and memory timing optimization.
• Understanding of ACPI, AMD STAPM, Intel DPTF, platform telemetry, Git, CI/CD, and agile workflows.
• Prior collaboration with AMD, Intel, or Arm on pre-silicon or early-silicon bring-up.

Culture & Benefits

• Close daily collaboration with Systems, Hardware, and Design/Applications Engineers in a fast-paced lab environment.
• Access to pre-production hardware, silicon support, and a dedicated debug lab with industry-standard instrumentation.
• Flexible work arrangements and professional development support.
• Health, dental, and vision coverage, 401(k) with company match, ESPP, paid holidays, paid time off, bonuses, and life and disability protection.
• Occasional travel to vendor or customer sites may be required.