aipci expressverilogsystemveriloglow power designrtl designtiming closuredigital ic designclock domain crossing
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Очень мало
$101к-162к/год
$140к$160кмедиана$190к
По похожим ролям (50) ~ $160к/год
На СНГ рынке: $1.9к/мес ($1.8к - $3к)
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Company hidden предлагает четко определенную senior-позицию в сильном направлении полупроводников и AI-инфраструктуры, но указанная зарплата заметно ниже рыночного ориентира, а работа только в офисе.
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Ниже рынкаТолько офисАктуальные технологииПерспективное направлениеПонятные задачи
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
RTL IC Design Engineer (AI/ML): Developing high-performance Verilog/SystemVerilog RTL for PCIe switch and enterprise storage products with an accent on micro-architecture, low-power design, clock-domain crossings, and pipelining. Focus on optimizing RTL for timing closure, debugging complex designs, integrating third-party IP, and supporting silicon validation.
Location: Colorado Springs, Colorado, United States; must work in person with no remote work allowed.
Annual base salary: USD 101,000–162,000.
Company
hirify.global develops semiconductor and infrastructure technology, including PCIe switch and enterprise storage products for data center and AI/ML ecosystems.
What you will do
Analyze, author, and review high-level architecture specifications.
Develop and document micro-architectures.
Implement high-quality, high-performance Verilog/SystemVerilog RTL from design specifications, including asynchronous clock-domain crossings, multiple power domains, low-power designs, complex algorithms, deep computations, pipelining, multi-threaded designs, and third-party IP integration.
Optimize RTL to achieve timing closure and debug designs with robust solutions.
Collaborate with Verification, Software/Firmware, Emulation, and Validation Engineering teams on RTL issues.
Provide lab support as silicon progresses through validation.
Requirements
Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering, or an equivalent engineering discipline.
5+ years of relevant industry experience.
In-depth knowledge of RTL design implementation and support using Verilog/SystemVerilog.
Nice to have
PCIe protocol experience.
CXL protocol experience.
AMBA protocol experience.
RAID storage design experience.
PCIe switch design experience.
Culture & Benefits
Full-time employment with medical, dental, and vision plans.
401(k) participation with company matching, Employee Stock Purchase Program, and equity awards.
Discretionary annual bonus.
Company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leaves.
Employee Assistance Program.
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