Semiconductor Test Engineering Team Leader (AI)

Location: Bristol, United Kingdom

Company

hirify.global develops custom chips and systems for high-speed inference of frontier AI models, focusing on AI accelerators capable of generating thousands of tokens per second.

What you will do

• Drive manufacturing test strategy and production readiness for AI accelerator chips featuring PCIe Gen6, LPDDR, advanced CMOS nodes, and 2.5D/3D or chiplet packaging.
• Lead chip test engineers responsible for test planning, program development, pattern bring-up, silicon characterization, debug, and optimization.
• Manage OSATs, ATE vendors, and external engineering partners, including scope definition, technical oversight, scheduling, and quality control.
• Define test software architecture, DFT usage, and structural and functional test content for logic, SRAM, DRAM, and high-speed I/O.
• Lead ATE silicon bring-up, correlation, failure analysis, shmooing, corner and stress testing, and yield improvement.
• Develop metrics and continuous improvements for test coverage, yield, test time, cost, automation, data analytics, and advanced packaging test flows.

Requirements

• At least 8 years of semiconductor test engineering experience, including leadership or technical lead responsibilities.
• Deep ATE test development experience with platforms such as Advantest 93K or Teradyne.
• Strong knowledge of DFT, including scan, ATPG, LBIST, and MBIST, as well as memory and high-speed interface testing.
• Experience managing external test development partners or OSATs and leading test engineering teams.
• Background in advanced CMOS nodes, silicon debug, characterization, and correlation between ATE and system-level environments.
• Ability to collaborate with design, architecture, product engineering, packaging, validation, and operations teams.

Nice to have

• Experience with AI/ML accelerator chips or other high-performance compute ICs.
• PCIe Gen5/Gen6 or LPDDR4/5/6 test methodology experience.
• Signal-integrity-aware test development and high-speed I/O margining experience.
• Experience with chiplets, 2.5D/3D IC test flows, or heterogeneous integration.

Culture & Benefits

• High ownership and autonomy in driving work from concept to hardware.
• Direct collaboration with senior leadership and close engagement across hardware, software, silicon, and modelling teams.
• Private medical, dental, and vision coverage.
• Contributory pension, 25 days of holiday plus bank holidays, and life and critical illness insurance.
• Meaningful equity and an inclusive, diverse office environment.