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10 часов назад

Technical Staff Engineer - Design (FPGA Fabric)

91 000 - 232 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Technical Staff Engineer - Design (FPGA Fabric) (FPGA Fabric/Custom Circuit Design): Designing and optimizing FPGA Fabric architecture for advanced, low-power FPGA devices with an accent on interconnect, routing, logic elements, memory, clocking, performance, power, and area. Focus on SPICE-based circuit analysis, Verilog modeling, mixed-signal EDA, timing and yield characterization, and silicon validation.

Location: San Jose, California, United States; onsite

Annual base salary: $91,000–$232,000, plus restricted stock units and quarterly bonuses.

Company

hirify.global develops embedded control, FPGA, microcontroller, processor, memory, connectivity, power management, and other semiconductor products.

What you will do

  • Design and develop FPGA Fabric architecture, including interconnect, routing muxes, logic elements, memory blocks, clocking, and related components.
  • Analyze and optimize performance, power consumption, area utilization, yield, reliability, and other design metrics.
  • Create and verify circuit schematics and functional Verilog models, comparing simulation results with SPICE-based models.
  • Collaborate with architecture, ASIC, firmware, verification, test, layout, timing characterization, and software model teams.
  • Prepare specifications, design documents, test plans, and formal design reviews.
  • Support verification and timing characterization and participate in silicon validation of FPGA Fabric blocks.

Requirements

  • Bachelor’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
  • 12+ years of experience in custom FPGA Fabric design and/or memory circuit design.
  • Strong SPICE simulation proficiency and experience with full-custom and mixed-signal EDA tools, parasitic extraction, simulations, and EM/IR analysis.
  • Experience with scripting, simulation queue management, data capture and analysis, yield impact, reliability, and power analysis.
  • Ability to support layout, verification, timing characterization, and software model development.
  • Strong analytical, communication, documentation, independent execution, and collaboration skills.

Nice to have

  • Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
  • Experience in analog, full-custom, FPGA, or ASIC development.
  • Experience in functional verification, timing characterization, and low-power design.
  • Experience with OCV timing and yield variation analysis using Solido and Monte Carlo methods.

Culture & Benefits

  • Full-time position with usual business hours and 0%–25% travel.
  • Health benefits beginning on day one and retirement savings plans.
  • Restricted stock units, quarterly bonus payments, and an employee stock purchase plan with a two-year look-back feature.
  • Culture focused on trust, empowerment, respect, diversity, communication, employee development, and long-term career growth.

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