Technical Staff Engineer - Design (FPGA Fabric)

Location: San Jose, California, United States. Onsite role with 0%–25% travel and usual business hours.

Annual base salary: $91,000–$232,000, plus restricted stock units and quarterly bonus payments.

Company

hirify.global is a corporation providing embedded control, FPGA, microcontroller, processor, memory, connectivity, power management, security, and related semiconductor products and Flash-IP solutions.

What you will do

• Design and develop FPGA Fabric architecture, including interconnect, routing muxes, logic elements, memory blocks, clocking, and other key components.
• Analyze and optimize FPGA Fabric for performance, power consumption, area utilization, yield, reliability, and other relevant metrics.
• Create and verify circuit schematics and functional Verilog models, compare Verilog simulation models with SPICE-based models, and support circuit-block design and verification beyond FPGA Fabric.
• Collaborate with system architects and hardware, ASIC, firmware, software, verification, timing characterization, layout, and test teams to integrate FPGA Fabric with processors, interfaces, peripherals, and overall product requirements.
• Prepare specifications, design documents, test plans, and formal reviews; manage simulation queues, data capture, and analysis.
• Support verification and timing characterization and drive silicon validation of FPGA Fabric blocks for functionality and performance.

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
• 12+ years of experience in custom FPGA Fabric design and/or memory circuit design.
• High proficiency with SPICE simulation and full-custom and mixed-signal EDA tools for parasitic extraction, simulations, and EM/IR analysis.
• Competency in scripting, simulation queue management, data capture, and analysis.
• Proficiency in simulating and analyzing yield impact, reliability, and power.
• Ability to support layout, verification, timing characterization, and software model developers.
• Ability to develop and test Verilog simulation models and compare them with SPICE-based models.
• Excellent written and verbal communication, analytical, and documentation skills.
• Self-motivated, proactive, detail-oriented, able to work independently, collaborate as a team player, and drive tasks to completion on time.

Nice to have

• Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
• Experience in analog and full-custom design, FPGA or ASIC development, functional verification, and timing characterization.
• Experience with low-power design, including dual rail, array biasing, dynamic low-power mode switching, sleep, power gating, and column array muxing.
• Experience with OCV timing and yield variation analysis using Solido and Monte Carlo.

Culture & Benefits

• Work within a large global organization focused on trust, empowerment, respect, diversity, communication, employee development, and community.
• Health benefits begin on the first day of employment.
• Benefits include retirement savings plans and an employee stock purchase program with a two-year look-back feature.
• Total compensation includes base pay, restricted stock units, and quarterly bonus payments.