Senior Analog Design Engineer (SerDes)

Company

hirify.global is a hardware and software innovation company focused on unleashing the potential of generative AI through advanced inference accelerators.

What you will do

• Own transistor-level design of SerDes transmit paths, including output drivers, pre-drivers, and serializers.
• Design receive front-end components such as termination networks, CTLE, VGA, and samplers.
• Develop and verify equalization paths, including DFE and FFE architectures and adaptation behavior.
• Perform link and channel modeling using MATLAB or Python to ensure BER targets are met.
• Drive block layout in deep sub-micron nodes, collaborating with backend and signal-integrity engineers.
• Conduct silicon bring-up and bench characterization to correlate measured performance with simulation.

Requirements

• BS/MS/PhD in Electrical Engineering with 8+ years of hands-on analog and mixed-signal circuit design experience.
• Proven track record of taking SerDes datapath blocks through to working silicon.
• Deep expertise in high-speed driver design, receive front-end design, and equalization.
• Proficiency in jitter and noise analysis, including decomposition and budgeting.
• Experience with advanced FinFET or GAA process nodes and industry-standard tools like Cadence Virtuoso and Spectre.
• Must be based in or able to work from Santa Clara, CA (Hybrid role).

Nice to have

• Experience with die-to-die interconnects (UCIe, BoW) and PAM4 signaling.
• Familiarity with standards such as OIF CEI-112G/224G, PCIe Gen6/Gen7, and IEEE 802.3.
• Experience with IBIS-AMI model generation or production test development.

Culture & Benefits

• Competitive compensation package including salary, equity, and bonus opportunities.
• Comprehensive benefits including Medical, Dental, Vision, and 401(k).
• Inclusive and collaborative culture that values humility and direct communication.
• Opportunity to work at the forefront of generative AI hardware transformation.