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24 часа назад

Senior Distinguished Engineer (ASIC Architecture)

242 350 - 363 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior Distinguished Engineer (ASIC Architecture): Architecting next-generation high-performance networking switch ASICs and multi-die chiplet systems with an accent on performance, scale-out capabilities, power efficiency, and silicon leadership. Focus on designing die-to-die interconnects, optimizing switching pipelines and memory subsystems, and driving complex products from concept through delivery.

Location: Full onsite collaboration in Santa Clara, California, United States

Salary: $242,350–$363,000 per annum

Company

hirify.global develops semiconductor solutions and networking technology for enterprise, cloud, AI, 5G, carrier, and hyperscale data-center infrastructures.

What you will do

  • Serve as principal architect for advanced networking ASICs focused on performance, scale-out capabilities, power efficiency, and silicon leadership.
  • Define long-term architectural roadmaps for next-generation switching platforms serving AI clusters, hyperscale cloud, carrier, and enterprise markets.
  • Architect multi-die systems, high-bandwidth die-to-die interconnects, and chiplet-based architectures.
  • Partner with hardware, software, packaging, validation, and systems engineering teams to deliver system-level solutions.
  • Represent architecture in executive technical reviews and customer engagements.
  • Mentor engineers and promote technical innovation and engineering excellence.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 15+ years of experience in ASIC architecture and design, preferably in networking, switching, or high-performance SoCs.
  • Experience leading complex ASIC or multi-die products from concept through delivery.
  • Deep expertise in networking ASIC architecture, multi-die systems, die-to-die protocols, chiplet integration, switching pipelines, memory subsystems, packet processing, traffic management, and buffer management.
  • Understanding of system software interaction, control-plane integration, and full-stack implications.
  • Eligibility to access U.S. export-controlled technology and software is required; export license review may apply.

Nice to have

  • Master’s degree or Ph.D.
  • Patents, publications, or other industry-recognized technical contributions.
  • Strong mentoring and senior-level communication experience.

Culture & Benefits

  • Engineering-led environment focused on creativity, technical rigor, and innovation.
  • Employee stock purchase plan with a two-year look-back.
  • Family support programs and mental health resources.
  • Recognition and service awards.
  • Comprehensive benefits supporting financial well-being, family support, and physical and mental health.

Hiring process

  • Interview process includes evaluation of individual experience, thought process, and communication skills.
  • AI tools, transcription applications, automated note-taking bots, and real-time answer generators are prohibited during interviews.

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