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1 день назад

Principal Post-Silicon Validation Engineer

180 000 - 255 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal Post-Silicon Validation Engineer (AI hardware): Owning post-silicon bring-up, debug, and validation for high-speed IO and memory subsystems in the DataScale platform with an accent on characterization, stress testing, performance analysis, and system-level root-cause investigation. Focus on validating PCIe, Ethernet, HBM, CXL, or UCIe interfaces, building automated debug tooling, and driving issues across silicon, board, and software layers through field deployment.

Location: San Jose, California, United States

Salary: $180,000–$255,000 USD base salary range

Company

hirify.global develops the hirify.global Suite, a full-stack generative AI platform built around its SN40L chip and designed for on-premises and cloud enterprise and government deployments.

What you will do

  • Own post-silicon bring-up and validation of high-speed IO and memory subsystems across characterization, functional validation, stress testing, and performance analysis.
  • Establish first-silicon power-on readiness, including debug infrastructure, tooling, and contingency planning.
  • Lead system-level debugging across silicon, board, and software layers, driving complex issues to root cause and closure.
  • Coordinate resolution with design, firmware, verification, and system engineering teams to maintain bring-up schedules.
  • Partner with system and customer engineering on product validation, deployment, and RMA debugging.
  • Own validation sign-off, review SoC and board designs, contribute to pre-silicon verification, and build automation for scalable test coverage.

Requirements

  • M.S. in Electrical Engineering, Computer Science, or a related field.
  • 7+ years of experience in post-silicon validation or system bring-up.
  • Experience with at least two high-speed IO or memory protocols, such as PCIe, Ethernet, HBM, CXL, or UCIe.
  • Proven ability to lead cross-functional debugging efforts through root cause and resolution.
  • Strong analytical skills for test development and data analysis.
  • Proficiency in Python and Bash scripting, with clear communication and a collaborative problem-solving approach.

Nice to have

  • Deep understanding of high-speed SerDes training and adaptation.
  • Experience with mixed-signal IO design and validation or optical interconnects.
  • Hands-on experience with oscilloscopes, protocol analyzers, and BERTs.
  • Ability to read and debug C/C++.

Culture & Benefits

  • Cross-functional collaboration with design, firmware, verification, system, and customer engineering teams.
  • Full-time US employment with equity and benefits.
  • Medical insurance coverage with 95% of employee premiums and 77% of dependent premiums covered.
  • Dental, vision, disability, life, AD&D, HSA, and FSA options.
  • Well-being benefits including Headspace, Gympass+, One Medical, and counseling services.

Hiring process

  • Submit a separate application form for each position.

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