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3 часа назад

Senior/Tech Lead Silicon Validation Engineer

148 500 - 165 000$
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior/Tech Lead Silicon Validation Engineer (AI connectivity semiconductors): Developing and executing electrical post-silicon validation tests for ICs and board products supporting high-speed AI infrastructure, with an accent on parametric performance, margin analysis, and system robustness. Focus on automating validation, debugging complex SoCs and SerDes interfaces, root-causing unexpected behavior, and certifying PCIe and Ethernet product compliance.

Location: California, United States

Salary: $148,500–$165,000 USD annually for Senior level; $175,000–$195,000 USD annually for Staff level

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions based on CXL, Ethernet, NVLink, PCIe, UALink, and its COSMOS software suite.

What you will do

  • Formulate comprehensive post-silicon validation plans for ICs and board products.
  • Automate electrical testing and execute validation across system conditions.
  • Design experiments to debug and root-cause unexpected silicon and system behavior.
  • Measure parametric device performance, margins, robustness, and specification compliance.
  • Report validation results and certify product parametric conformance.
  • Collaborate with internal customers to quantify margins and address requirements.

Requirements

  • Bachelor’s degree in Electrical or Computer Engineering; a Master’s degree is preferred.
  • At least 3 years of experience testing, supporting, or developing complex SoC or silicon products and high-speed IO/SerDes interfaces for server, storage, or networking applications.
  • Experience debugging and bringing up complex SoCs with high-speed interfaces such as PCIe and Ethernet.
  • Strong Python scripting and object-oriented programming skills, with basic DevOps knowledge using Git.
  • Knowledge of PLLs, CTLE, DFE, Tx EQ, NRZ, and PAM4 signaling.
  • Proficiency with high-speed laboratory equipment including BERTs, oscilloscopes, and VNAs.

Nice to have

  • Experience with system testing, characterization, margin analysis, and optimization of multi-gigabit data links.
  • Signal integrity experience related to PCIe, Ethernet, CEM, and NVMe interfaces.
  • Working knowledge of C or C++ for embedded firmware and serial interfaces such as I2C and SPI.
  • Experience with MATLAB, Keysight ADS, or PLTS for electrical-channel and signal-integrity analysis.

Culture & Benefits

  • Customer requirements and product robustness are treated as primary priorities.
  • An entrepreneurial, open-minded, and independent problem-solving approach is expected.
  • Diverse ideas, backgrounds, and experiences are actively encouraged.

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