RTL Design Engineer (AI)

Location: Austin, TX or Palo Alto, CA; hybrid

Salary: $120,000–$225,000+ annually

Company

hirify.global develops analog AI computing technology for edge devices, cloud, and data center environments, including applications in robotics, industrial systems, automotive, aerospace, and defense.

What you will do

• Design and implement RTL for next-generation AI processors.
• Develop and optimize high-performance, low-power datapaths, controllers, memory subsystems, and interconnects.
• Define microarchitecture with architecture teams and ensure functional correctness with verification engineers.
• Drive timing closure in collaboration with synthesis and physical design teams.
• Participate in design reviews and improve RTL coding practices and methodologies.

Requirements

• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
• 3+ years of industry experience in RTL design, microarchitecture, and architecture development.
• Understanding of pipelines, caches, coherence, memory hierarchies, and computer architecture fundamentals.
• Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
• Familiarity with timing constraints, physical design considerations, EDA flows, simulation, synthesis, linting, and static timing analysis.
• Strong problem-solving and communication skills for cross-functional collaboration.

Culture & Benefits

• Collaborative and respectful working environment.
• Tools, support, and autonomy to deliver meaningful work.
• Team culture focused on professionalism, creativity, integrity, and inclusion.
• Opportunity to work on challenging AI hardware and custom dataflow architecture.