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1 день назад

Senior Testchip SoC Physical Design Engineer (Integration & Methodology)

141 910 - 200 340$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Мэтч & Сопровод

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Описание вакансии

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TL;DR

Senior Testchip SoC Physical Design Engineer (Semiconductors): Developing layout design methodologies and driving full-chip SoC integration for cutting-edge testchip vehicles with an accent on physical design convergence and hierarchical layout specifications. Focus on solving complex layout constraints in advanced process nodes and ensuring high-quality, scalable solutions for manufacturing readiness.

Location: Hybrid (US: Hillsboro, Santa Clara, or Austin)

Salary: $141,910 – $200,340 USD

Company

hirify.global is a global leader in semiconductor innovation, focusing on the design and manufacturing of advanced chips for computing and data processing.

What you will do

  • Develop layout design methodologies for testchip development in next-generation process nodes.
  • Define critical design features in collaboration with Process Integration, Yield, and QnR teams.
  • Establish and maintain hierarchical layout design specifications for correct-by-construction integration.
  • Drive physical design convergence, prepare layout hierarchy for design tape-in, and resolve verification tool issues.
  • Collaborate with tool owners and vendors to drive continuous improvement in layout productivity and efficiency.

Requirements

  • Master's degree in Electrical Engineering or a related field.
  • Minimum 5 years of experience in physical/layout design within advanced technology nodes.
  • Proficiency in layout design tools such as Cadence Virtuoso Suite or Synopsys Custom Compiler.
  • Experience with floorplanning, hierarchical design integration, and layout verification/debug.
  • Must be based in the United States (specifically Oregon, California, or Texas).

Nice to have

  • Experience in defining Testchip/Product design from concept to execution commit.
  • Proven project management skills in coordinating the entire design cycle up to final tape-in.
  • Previous work experience within a semiconductor foundry.

Culture & Benefits

  • Hybrid work model allowing a split between on-site and off-site work.
  • Competitive compensation package including stock bonuses.
  • Comprehensive health, retirement, and vacation benefit programs.
  • Opportunities for technical leadership and career growth within an industry-leading expert environment.

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