Senior Digital/AMS Validation and Integration Engineer (Automotive SerDes)

Location: San Jose, California, United States

Salary: $166,200–$228,500 annually

Company

hirify.global develops semiconductor solutions for automotive and other technology applications.

What you will do

• Design and integrate Verilog/SystemVerilog RTL for control loops, calibration engines, and high-speed data paths in 10G+ automotive SerDes transceivers.
• Define digital interfaces to ADCs, PLLs, driver stages, and other analog front-end blocks, including signal crossing between asynchronous domains.
• Lead synthesis and digital implementation activities through timing closure in high-speed clock domains.
• Support silicon bring-up and validation using Python-based tools, logic analyzers, high-speed scopes, and JTAG/I2C/SPI interfaces.
• Run block-level and chip-level simulations to verify control logic, startup sequences, and behavior across analog PVT variations.

Requirements

• BSEE or MSEE with 5–8+ years of experience in digital RTL design or digital integration.
• Advanced proficiency in SystemVerilog and Verilog for synthesis.
• Strong knowledge of static timing analysis, clock domain crossing, and SDC constraints.
• Deep experience with Python or Perl for hardware control, test automation, and data processing.
• Proficiency with logic analyzers, high-speed oscilloscopes, and JTAG/I2C/SPI protocols for on-chip debugging.
• Base salary information is specific to California.

Nice to have

• Experience with 10GBase-T, ASA, or Automotive Ethernet standards.
• Experience interfacing digital logic with high-speed analog front ends.
• Knowledge of DFT and BIST insertion for high-speed links.
• Ability to create Verilog-A models.

Culture & Benefits

• Health, dental, and vision insurance.
• 401(k) plan and paid leave.
• Competitive benefits and incentive compensation; equity may be available for certain roles.
• Individual total compensation may vary based on qualifications, skills, work location, and organizational needs.