Senior Design Engineer (Verilog/SystemVerilog)

Location: Petah-Tikva, Israel

Company

hirify.global develops semiconductor solutions and data-infrastructure technologies for enterprise, cloud, AI, and carrier architectures.

What you will do

• Own one or more key digital blocks for next-generation network switches.
• Lead block design from architecture definition through implementation.
• Optimize area, timing, and power across the design flow.
• Perform linting and CDC/RDC analysis.
• Collaborate with verification engineers on block-level verification and design-verification alignment.

Requirements

• Bachelor’s or master’s degree in Electrical Engineering.
• 5+ years of relevant digital design experience.
• Proficiency in RTL design using Verilog or SystemVerilog.
• Experience with linting, CDC/RDC, synthesis, timing closure, power optimization, and backend flows.
• Strong problem-solving, analytical, collaboration, and communication skills.
• Applicants must be eligible to access export-controlled technology and software; an export license review may be required.

Nice to have

• Verification experience with SystemVerilog and UVM.
• Ability to quickly understand complex systems.

Culture & Benefits

• Full-time employment with competitive compensation and benefits.
• Collaborative, transparent, and inclusive work environment.
• Resources and support for professional growth and development.
• Interviews are intended to assess individual experience, reasoning, and communication; unauthorized AI tools are not permitted during interviews.