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7 часов Π½Π°Π·Π°Π΄

Design Engineer I (Embedded)

78Β 750 - 146Β 250$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
hybrid
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
junior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

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TL;DR

Design Engineer I (Embedded): Designing and verifying digital blocks for low-power wireless products with an accent on RTL implementation and digital system performance. Focus on building efficient digital architectures, resolving design issues, and contributing to the integration of modules within complex SoC designs.

Location: Must be based in or able to work from Austin, Texas (Hybrid)

Salary: $78,750–$146,250 USD

Company

hirify.global is a leading innovator in low-power wireless connectivity, providing integrated SoCs and ecosystems for smart home, industrial IoT, and smart city applications.

What you will do

  • Design, model, and verify digital blocks for low-power wireless products.
  • Develop RTL implementations and verification environments to ensure high performance and quality.
  • Collaborate with cross-functional teams to translate system requirements into efficient digital architectures.
  • Debug and resolve design and verification issues throughout the development cycle.
  • Contribute to the integration, bring-up, and validation of digital modules within SoC designs.
  • Develop scripts and tools to improve design, verification, and testing efficiency.

Requirements

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
  • Experience with RTL design using Verilog or SystemVerilog.
  • Understanding of digital design fundamentals including synchronous design, state machines, and timing.
  • Experience with digital design simulation and verification methodologies.
  • Basic programming skills in Python or MATLAB for automation and data analysis.

Nice to have

  • Knowledge of Digital Signal Processing (DSP) concepts and wireless communication standards (Bluetooth, Zigbee, Thread, Wi-Fi).
  • Experience with MATLAB modeling for DSP algorithms.
  • Exposure to ASIC/SoC design flows (synthesis, linting, CDC analysis).
  • Experience with FPGA development or hardware bring-up.

Culture & Benefits

  • Comprehensive medical, dental, and vision plans with HSA options.
  • 401k plan with company match and equity rewards (RSUs).
  • Flexible PTO schedule and 3 paid volunteer days per year.
  • Tuition reimbursement and adoption assistance.
  • Onsite gym, free snacks, and downtown parking.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’