Lead Design Engineer - Verification (VLSI)

TL;DR

Lead Design Engineer - Verification (VLSI): Developing and executing verification plans for SOC and IP blocks with an accent on UVM and SystemVerilog. Focus on RTL verification, protocol integration, and ensuring comprehensive test coverage for high-quality SOC delivery.

Location: Shanghai

Company

hirify.global is a leading provider of intelligent systems design software, hardware, and IP.

What you will do

• Develop and execute verification plans for SOC and IP blocks to ensure design intent and testability.
• Perform RTL verification using industry-standard methodologies including UVM and SystemVerilog.
• Collaborate with design engineers to address complex debug issues and optimize verification strategies.
• Work with customers and internal engineering teams to deliver high-quality support and service.
• Participate in coverage analysis, regression testing, and closure of verification goals.
• Contribute to the development and enhancement of verification environments and reusable testbenches.

Requirements

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field.
• 3–5 years of professional experience in VLSI/SOC design verification.
• Strong expertise in System Verilog, UVM, and industry-standard verification tools.
• Hands-on experience with protocols such as AMBA, PCIe, USB, MIPI, or DDR/LPDDR.
• ARM/RISC-V Processor integration experience is preferred.