4 дня назад
Design Verification Senior Staff Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Design Verification Senior Staff Engineer (ASIC/RTL, SystemVerilog/UVM): Driving functional verification of complex networking blocks and developing advanced verification components and testbenches for next-generation network switches with an accent on coverage-driven verification and constrained random testing. Focus on building verification infrastructure, collaborating across architecture, design, firmware, and post-silicon teams, and improving verification methodologies.
Location: Petah-Tikva, Israel
Company
develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure, including next-generation network switches.
What you will do
- Drive functional verification of complex networking blocks using SystemVerilog and UVM.
- Develop and maintain advanced verification components and testbenches.
- Verify IPs for switching products across definition, architecture, design, and verification stages.
- Collaborate with architecture, design, firmware, and post-silicon teams.
- Improve verification methodologies and infrastructure.
Requirements
- B.Sc. or M.Sc. in Electrical or Computer Engineering.
- 7+ years of hands-on ASIC/RTL verification experience.
- Strong SystemVerilog and UVM methodology skills.
- Deep understanding of coverage-driven verification, object-oriented programming, and constrained random testing.
- Excellent problem-solving and self-learning abilities.
- Eligibility to access export-controlled technology may be required; applicants may be subject to an export license review.
Culture & Benefits
- Competitive compensation and benefits.
- Collaborative, transparent, and inclusive work environment.
- Resources and opportunities for professional growth and development.
- Interviews prohibit the use of AI tools unless explicitly authorized.
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