Design Verification Engineer (ASIC)

Location: On-site in San Jose, United States

Salary: $150,000–$275,000 per year, plus significant equity

Company

hirify.global builds frontier AI hardware by co-designing chips, racks, software, and manufacturing systems focused on high-throughput, low-latency inference.

What you will do

• Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMA engines, NoCs, and memory subsystems.
• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
• Debug complex datapath and protocol issues in RTL and testbench environments.
• Collaborate with architects and RTL designers to validate functionality and design intent.
• Partner with software, firmware, and emulation teams on end-to-end bring-up and debug coverage.
• Improve reusable design verification infrastructure, coverage models, and methodologies.

Requirements

• Proficiency with UVM and SystemVerilog.
• Strong debugging and problem-solving skills for complex digital designs.
• Knowledge of computer architecture and digital design fundamentals.
• Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
• Ability to work fully in person in San Jose and contribute across engineering and research disciplines.

Nice to have

• Experience with SystemVerilog Assertions and formal verification techniques.
• Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
• Scripting skills in Python, Perl, TCL, or similar languages for automation, debugging, and regression flows.

Culture & Benefits

• Medical, dental, and vision coverage with generous premium support.
• $500 monthly credit for waiving medical benefits.
• $2,000 monthly housing subsidy for employees living within walking distance of the office.
• Relocation support for moving to San Jose.
• Wellness benefits, daily lunch and dinner at the office, and an unlimited compute budget subject to ROI justification.
• Fully in-person collaboration with no strict separation between engineering and research.