Digital IP Principal Verification Engineer (SystemVerilog/UVM)

TL;DR

Digital IP Principal Verification Engineer (SystemVerilog/UVM): Defining and implementing verification strategies for IP and sub-system levels with an accent on functional verification and testbench environment development. Focus on writing UVM stimulus, SVA cover properties, and utilizing AI to optimize work product generation.

Location: Must be based in the Austin (Oakhill) office

Company

hirify.global is a global leader in secure connectivity solutions for embedded and automotive applications.

What you will do

• Define and implement verification strategies and plans for IPs or sub-systems based on architecture specifications.
• Develop UVM-based testbenches, including stimulus, random test scenarios, and directed testcases.
• Create and verify SystemVerilog Assertions (SVA) to ensure functional correctness.
• Debug failing testcases across tools, testcases, and RTL to ensure resolution.
• Analyze code and functional coverage to achieve 100% coverage.
• Utilize AI tools to augment the generation of verification work products.

Requirements

• Must be based in or able to work from the Austin (Oakhill) office.
• BSEE, BSCE, or BSCS degree (MSEE/MSCE/MSCS preferred).
• Minimum 6 years of experience in IP or SoC design and verification.
• Proficiency in Verilog, SystemVerilog, and UVM.
• Strong skills in test planning, simulation, and debugging.
• Ability to work independently and in small teams without close supervision.

Nice to have

• Programming skills in Python, C/C++, Perl, or TCL.
• Experience with RTL coding, synthesis, and formal checkers.
• Knowledge of ARM AMBA protocols.

Culture & Benefits

• Equal Opportunity and Affirmative Action employer.
• Reasonable accommodations provided for qualified disabled individuals.
• Opportunity to work within a high-tech environment at a leading semiconductor corporation.