Design Verification Engineer

Location: On-site in Sunnyvale, California, United States

Salary: $190,000–$230,000 annually, plus potential bonus and equity

Company

Builds large-scale AI chips and computing systems designed to deliver high-speed model training and inference.

What you will do

• Develop verification strategies, detailed tests, and coverage plans from micro-architecture specifications.
• Create reusable verification environments with stimulus, checkers, assertions, and coverage components.
• Implement tests, manage regressions, collect coverage, and debug failures.
• Analyze complex issues across simulation, emulation, and silicon bring-up.
• Collaborate with architecture, RTL design, physical design, firmware, post-silicon, software, and validation engineers.
• Improve verification infrastructure, flows, methodologies, and organization-wide best practices.

Requirements

• 3+ years of design verification experience.
• Deep knowledge of SystemVerilog testbenches, DPI, and UVM.
• Experience developing scalable and portable testbenches and verification components.
• Knowledge of simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulation.
• Strong programming skills, object-oriented design knowledge, and proficiency in Python or Perl scripting.
• Excellent debugging, problem-solving, interpersonal, and collaboration skills.

Nice to have

• Knowledge of pipelined processor architecture.
• BS or MS in Computer Science or Electrical Engineering.

Culture & Benefits

• Opportunity to build AI computing hardware beyond GPU constraints.
• Access to cutting-edge AI research, including publishing and open-source work.
• Work on high-performance AI supercomputing systems.
• Combination of startup vitality and job stability.
• Non-corporate culture focused on individual beliefs, learning, growth, and support.