Formal Verification Engineer (ASIC)

Location: On-site in San Jose, California, United States. Relocation support is available for candidates moving to San Jose.

Company

hirify.global builds custom chips, racks, software, and manufacturing systems for high-throughput, low-latency AI inference.

What you will do

• Define and drive formal verification strategy across complex ASIC IP blocks, interface subsystems, and SoC integration logic.
• Develop verification plans for functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
• Build reusable formal environments with SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
• Drive proof convergence and formal sign-off using abstraction, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics.
• Debug RTL, protocol, datapath, connectivity, and integration issues using formal counterexamples, waveforms, and design analysis.
• Collaborate with architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams to align verification, simulation, regressions, and chip bring-up.

Requirements

• 5+ years of design verification experience, including substantial hands-on formal verification of complex digital designs or shipping silicon.
• Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
• Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
• Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
• Ability to model complex behavior with assumptions, abstractions, constraints, cut-points, checkers, and reference models.
• Strong debugging and cross-functional collaboration skills across RTL, specifications, simulation, firmware, software, and verification reports.

Nice to have

• Formal verification experience with systolic arrays, DMA engines, NoCs, memory subsystems, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers.
• Experience with protocol, connectivity, register, datapath, reset, or deadlock/livelock verification.
• Experience with vendor IP integration, encrypted or black-box IP, VIP configuration, or contract-based subsystem verification.
• Experience with sequential LEC, arithmetic proofs, cache coherency, interrupt handling, or memory-mapped I/O verification.
• Scripting experience in Python, TCL, Perl, or similar languages for automation, regressions, debugging, and dashboarding.

Culture & Benefits

• Fully in-person engineering team based in San Jose, with technical staff contributing across engineering and research.
• Medical, dental, and vision coverage with generous premium support.
• $500 monthly credit for waiving medical benefits.
• $2,000 monthly housing subsidy for employees living within walking distance of the office.
• Wellness benefits covering fitness and mental health.
• Daily lunch and dinner served at the office.