23 часа назад
DFT Lead Engineer (ASIC)
143 800 - 230 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
DFT Lead Engineer (ASIC/SoC): Leading DFT programs from chip-level architecture and test insertion through verification, silicon bring-up, and production release with an accent on scan, MBIST, ATPG, boundary scan, and test-vector generation. Focus on closing DFT timing with physical design and STA teams, debugging ATE and silicon failures, improving yield, and automating DFT flows for 7nm and beyond.
Location: San Jose, California, USA
Annual base salary: USD 143,800–230,000, plus discretionary annual bonus and equity awards.
Company
's ASIC Product Division develops ASIC and SoC designs and related DFT solutions.
What you will do
- Lead DFT programs from chip-level specification and architecture through implementation, verification, and production release.
- Implement and verify Scan, MBIST, TAP, LBIST, IO, SerDes, and other IP DFT integrations.
- Generate, verify, and debug test vectors before tape release and during silicon bring-up on ATE.
- Work with physical design, STA, design integration, test engineering, manufacturing, IP DFT, and customer teams on test closure and product requirements.
- Support silicon failure analysis, diagnostics, customer-returned-part debugging, and yield improvement.
- Develop new DFT solutions and automate DFT and test-vector-generation flows for 7nm and beyond.
Requirements
- Strong DFT experience, including IO and analog DFT, ATPG, scan, BIST, scan insertion, and scan compression.
- Experience with ATPG vector generation, simulation, and debugging using tools such as TetraMax, Fastscan, DFT Compiler, or TestKompress.
- Experience with Verilog coding, testbench generation, simulation, MBIST insertion and verification, and boundary scan based on IEEE 1149.1 and IEEE 1149.6.
- Strong knowledge of IEEE 1687, IJTAG, ICL, PDL, test-STA, and timing constraints.
- Knowledge of analog and digital circuit design, device physics, silicon processing, logical and physical synthesis, and transistor reliability principles.
- Bachelor's degree in Electrical, Electronic, or Computer Engineering with 12+ years of relevant industry experience, or a master's degree with 10+ years of relevant experience.
Nice to have
- ATE experience and silicon debug experience with SerDes, DDR, PCIe, Ethernet, or CXL IOBIST.
- Experience with Tessent SSN.
Culture & Benefits
- Cross-disciplinary collaboration with globally located customer, physical design, test engineering, and manufacturing teams.
- Medical, dental, and vision plans.
- 401(k) participation with company matching and an Employee Stock Purchase Program.
- Paid holidays, sick leave, vacation time, and applicable paid family leave.
- Employee Assistance Program, annual bonus eligibility, and new-hire and annual equity awards.
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