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DFT Lead Engineer (ASIC)

143 800 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
DFT Lead Engineer (ASIC): Leading chip-level DFT architecture, implementation, verification, test-vector generation, and silicon debug for Broadcom ASIC products with an accent on Scan, MBIST, ATPG, boundary scan, and IJTAG. Focus on closing DFT timing, improving coverage and yield, debugging ATE and customer-returned parts, and automating test-vector generation for 7nm-and-beyond designs.

Location: San Jose, California, USA; onsite at hirify.global's development center

Annual base salary: USD 143,800–230,000, plus discretionary bonus and equity awards.

Company

hirify.global's ASIC Product Division develops ASIC products and SoC designs for customers across multiple industries.

What you will do

  • Lead DFT programs from chip-level specification through implementation, verification, tape release, and production.
  • Define DFT specifications based on product requirements, customer requirements, and DPPM targets.
  • Implement and verify Scan, MBIST, TAP, LBIST, IO, SerDes, and other IP-level DFT integrations.
  • Generate, verify, debug, and validate test vectors during silicon bring-up and ATE testing.
  • Support failure analysis, diagnostics, yield improvement, and debugging of customer-returned parts.
  • Collaborate with STA, physical design, test engineering, manufacturing, customers, and other DFT stakeholders while developing automated DFT flows.

Requirements

  • Strong DFT experience in IO and analog DFT, ATPG, Scan, BIST, and related areas.
  • Experience with scan insertion and compression tools such as DFT Compiler and TestKompress, and ATPG tools such as TetraMax or Fastscan.
  • Experience with Verilog, testbench development, simulation, MBIST, boundary scan, IEEE 1149.1, IEEE 1149.6, IEEE 1687, IJTAG, ICL, and PDL.
  • Knowledge of test-STA, timing constraints, analog and digital circuit design, synthesis, silicon processing, and transistor reliability.
  • Programming experience with TCL, Perl, Ruby, Python, C++, or similar languages.
  • Bachelor's degree and 12+ years of relevant industry experience, or a master's degree and 10+ years of relevant industry experience, in electrical, electronic, or computer engineering.

Nice to have

  • ATE experience and silicon debug.
  • Experience with SerDes, DDR, PCIe, ENET, CXL IOBIST, and Tessent SSN.

Culture & Benefits

  • Cross-disciplinary collaboration with globally located customer, physical design, test engineering, and manufacturing teams.
  • Medical, dental, and vision coverage.
  • 401(k) participation with company matching and an Employee Stock Purchase Program.
  • Paid holidays, sick leave, vacation, paid family leave, and other applicable leave programs.
  • Discretionary annual bonus, new-hire equity grants, and annual equity awards.

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