Power Integrity (PI) Engineer

Location

Location: San Jose (on-site)

Company

hirify.global builds hardware for frontier intelligence, co-designing chips, racks, software, and manufacturing to deliver high throughput and low latency for inference workloads.

What you will do

• Own power integrity methodology from early architecture through final release for high-power PCB and system designs.
• Run pre- and post-layout PDN analysis for high-current ASIC power rails, including target impedance profiling, decoupling optimization, and plane resonance/anti-resonance analysis.
• Perform DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation requirements.
• Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the full decoupling network.
• Develop and validate VRM models; analyze load transient response, AVP/load-line behavior, and multiphase converter performance.
• Support bring-up and debug of rail-level issues (droop, ripple, transient excursions) and maintain simulation-to-hardware correlation databases.

Requirements

• B.S. or M.S. in Electrical Engineering or a closely related discipline.
• 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery, server boards, or accelerator platforms).
• Proficiency with industry PI EDA tools (Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent).
• Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation.
• Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity.
• Working knowledge of VRM fundamentals (buck converter operation, multiphase design, transient response, load-line/AVP concepts) and multi-layer PCB stack-up/power plane allocation.

Nice to have

• Experience in data center, AI/ML accelerator, networking, or HPC hardware environments.
• Experience with vertical power delivery, high-current lateral delivery tradeoffs, or 48V-to-point-of-load architectures.
• Package-level PDN co-analysis and die/package power model work with ASIC teams.
• Ability to script automated PI simulation flows using Python or MATLAB.

Culture & Benefits

• Fully in-person team in San Jose (Santana Row).
• Medical, dental, and vision coverage with generous premium support.
• $500/month credit for waiving medical benefits.
• Housing subsidy of $2k/month for those living within walking distance of the office.
• Relocation support for moving to San Jose (Santana Row).
• Daily lunch and dinner in the office; unlimited compute budget subject to ROI justification.

Hiring process

• Not specified in the provided text.