обновлено 6 дней назад
Senior Analog Mixed-Signal Verification Engineer (Verilog-AMS)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Analog Mixed-Signal Verification Engineer (Verilog-AMS/PMIC): Leading analog and mixed-signal verification for automotive and industrial PMIC products from specification through verification signoff with an accent on behavioral modeling, constrained-random simulation, coverage, and regression automation. Focus on building reusable UVM and RNM environments, verifying power-management and fault-management functions, and solving complex verification challenges across blocks, subsystems, and SoCs.
Location: Chandler, Arizona, USA — office-based
Company
develops secure connectivity and embedded solutions for automotive, industrial, IoT, mobile, and communications applications.
What you will do
- Lead analog and mixed-signal verification for automotive and industrial PMIC products from requirements through signoff.
- Define verification plans, strategies, environments, regressions, coverage objectives, schedules, and milestone tracking.
- Develop behavioral models, checkers, assertions, scoreboards, and reusable verification components using Verilog-AMS, SystemVerilog, UVM, and RNM.
- Drive constrained-random verification, mixed-signal simulation, coverage analysis, regression management, debug, and signoff.
- Verify digital control, monitoring, telemetry, diagnostics, configuration, protection, power sequencing, and fault-management functions.
- Collaborate with analog, digital, validation, subsystem, SoC, applications, systems, and architecture teams while mentoring junior engineers.
Requirements
- M.S. in Electrical Engineering, Computer Engineering, or a related field.
- At least 10 years of experience in analog and mixed-signal IC verification and development, including technical leadership.
- Strong understanding of PMICs, DC-DC converters, LDOs, ADCs, DACs, PLLs, voltage references, bandgaps, and sensor interfaces.
- Expertise in Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling.
- Experience with coverage-driven and constrained-random verification, regression automation, verification signoff, and reusable verification environments.
- Proficiency with Cadence, Synopsys, and Siemens EDA tools, plus scripting in Python, Perl, Tcl, or Shell.
Nice to have
- Experience with formal verification, low-power verification, and requirements traceability methodologies.
Culture & Benefits
- Online and offline learning opportunities support technical and professional development.
- Cross-functional collaboration in a product development environment.
- Inclusive workplace with diversity, equality, and inclusion programs.
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