8 часов назад
Senior Digital Verification Engineer (SoC/ASIC)
160 000 - 210 000$
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Digital Verification Engineer (SoC/ASIC): Driving functional verification of complex SoC/IP designs from specification through tapeout with an accent on UVM-based testbench architecture, constrained-random verification, coverage closure, and simulation debug. Focus on building verification flows for multi-million-gate ASICs, automating regressions with Python, and evaluating formal, power-aware, and AI-agentic verification methods.
Location: San Jose, CA; Pittsburgh, PA; or Austin, TX
Salary: $160,000–$210,000 per year, plus equity and comprehensive benefits.
Company
is developing an energy-efficient, programmable general-purpose processor for continuous AI/ML at the edge and in IoT devices.
What you will do
- Drive functional verification of complex SoC and IP designs from specification through tapeout.
- Architect UVM-based testbenches and apply constrained-random verification methodologies.
- Drive functional and code coverage closure through tapeout sign-off for multi-million-gate SoC and ASIC designs.
- Debug complex simulation failures and develop verification models using C/C++.
- Build Python-based test automation, log analysis, coverage post-processing, and regression flows.
- Communicate verification risks, status, and tradeoffs to technical peers and program leadership.
Requirements
- Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of progressive ASIC/SoC design verification experience, including multiple full ownership cycles from testbench architecture through tapeout.
- Expertise in UVM, SystemVerilog, and constrained-random verification.
- Experience with C/C++ for modeling or verification and Python for automation.
- Demonstrated coverage-closure and complex simulation-debugging experience.
- Clear communication with technical peers and program leadership.
Nice to have
- Formal verification experience with JasperGold or a similar tool.
- Experience building or using AI agentic flows for design verification.
- Software/firmware-based testing, pre-silicon collaboration with software teams, and post-silicon experience.
- Knowledge of processors, ARM, RISC-V, AMBA AXI/ACE/CHI, memory controllers, DMA engines, interrupt controllers, and standard peripherals.
- Power-aware verification and UPF experience.
Culture & Benefits
- Competitive compensation with meaningful equity.
- 401(k) match and company-paid benefits.
- Paid parental leave.
- Flexibility and support for personal and professional development.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →