RTL Engineer (ASIC)

Location: On-site in San Jose, California

Salary: $150,000–$275,000 per year plus significant equity

Company

hirify.global builds inference-focused AI hardware by co-designing chips, racks, software, and manufacturing systems to optimize throughput and latency.

What you will do

• Develop and implement design verification strategies for current and upcoming ASIC designs.
• Implement RTL blocks for efficient floating-point mathematical operations.
• Work with machine-learning hardware architectures and learn transformer-related concepts.
• Provide feedback to the microarchitecture team to help blocks meet timing and area constraints.
• Contribute across engineering and research disciplines with a high degree of autonomy.

Requirements

• At least 5 years of professional RTL development experience.
• Experience with high-speed digital logic.
• Proficiency with standard RTL design and synthesis tools.
• Familiarity with verification work and writing test benches.
• Ability to learn quickly about transformers and modern artificial intelligence.
• Willingness to start quickly and work fully in person in San Jose.

Nice to have

• Experience with PCIe, Ethernet, or HBM technologies.
• Familiarity with modern ML and LLM model architectures.
• Knowledge of numerical representations and functions.
• Ability to program in Python or another scripting language.

Culture & Benefits

• Medical, dental, and vision coverage with generous premium support.
• $500 monthly credit for waiving medical benefits.
• $2,000 monthly housing subsidy for employees living within walking distance of the office.
• Relocation support for those moving to San Jose.
• Wellness benefits, daily lunch and dinner, and an ROI-justified unlimited compute budget.
• Fully in-person work with cross-disciplinary collaboration between engineering and research.