Назад
19 часов назад

Staff SoC Design Engineer ML ASIC Design Engineer ASIC Design Verification Engineer ML Accelerator Architect Systems Integration Engineer

251 000 - 310 000$
Формат работы
onsite/hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Staff SoC Design Engineer (ASIC/ML Accelerators): Architecting and implementing next-generation autonomous vehicle SoCs, including cache and memory hierarchies, NoC interconnects, and custom accelerators, with an accent on high-performance digital design and hardware-software interaction. Focus on microarchitecture, power-area-performance optimization, third-party IP integration, and driving ASIC designs through successful tapeout and production.

Location: Mountain View, California; on-site/hybrid role

Salary: $251,000–$310,000 USD per year, plus annual bonus, equity incentives, and company benefits.

Company

Waymo develops autonomous driving technology and the compute platforms powering fully autonomous vehicle software.

What you will do

  • Define architecture and microarchitecture for next-generation autonomous vehicle SoCs and translate system requirements into hardware specifications and RTL.
  • Lead the design and implementation of major IPs and subsystems, including cache and memory hierarchies, NoC interconnects, and custom accelerators.
  • Collaborate with architecture, firmware, and software teams to drive feature closure and develop microarchitecture specifications.
  • Explore and optimize digital designs for power, area, and performance.
  • Mentor engineers, guide external vendor relationships, evaluate third-party IP, and support successful tapeout and product delivery.

Requirements

  • MS degree in Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience.
  • 10+ years of industry experience in ASIC/SoC digital design, microarchitecture, and integration.
  • Ownership of major design blocks or subsystems and multiple successful ASIC tapeouts.
  • Deep expertise in SystemVerilog for RTL design, microarchitecture, and integration.
  • Strong knowledge of computer architecture, memory systems, cache coherence, and high-speed on-chip interconnects.
  • Fluency in Python or C++ and strong debugging skills across hardware and software boundaries.

Nice to have

  • PhD in Computer Engineering, Electrical Engineering, or a related field.
  • Hardware/software co-design experience with DSPs, GPUs, or ML accelerators.
  • Knowledge of arithmetic units, processor design, bus architectures, fabrics/NoC, memory hierarchies, and low-power design.
  • Experience with AI tools, Chisel, Scala, or other hardware DSLs for RTL generation.

Culture & Benefits

  • Work with a multidisciplinary Compute Team building a high-performance automotive compute platform.
  • Collaborate across hardware, firmware, software, architecture, and external vendor teams.
  • Eligibility for a discretionary annual bonus, equity incentive plan, and company benefits program.

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