Physical Design Engineer (AI Accelerator IP)

Location: Hybrid, based out of Toronto, Ontario, Canada; Austin, Texas, United States; or Belgrade, Serbia

Salary: $100,000–$500,000 annually, including base and variable compensation targets.

Company

Tenstorrent develops and licenses high-performance RISC-V CPU and AI accelerator IP, software, compilers, platforms, networking, and semiconductor technologies.

What you will do

• Own the physical implementation of IP blocks from synthesis through place-and-route, timing closure, and GDSII signoff.
• Drive PPA outcomes by closing critical paths and meeting power budgets in collaboration with RTL owners.
• Build floorplans, power grids, pin placements, and clocking strategies for advanced-node designs.
• Deliver IP integration collateral, including LEF/DEF files, timing and power models, GDS, and signoff reports.
• Port IP across process nodes, foundries, and PPA targets while supporting customer delivery timelines.
• Collaborate with architecture, RTL, and chiplet integration teams on front-to-back co-design.

Requirements

• BS, MS, or PhD in EE, ECE, CE, CS, or a related field.
• 5+ years of block-level or IP-centric physical design experience through tapeout.
• Hands-on experience with Innovus, ICC2/Fusion Compiler, and PrimeTime.
• Proficiency in Tcl, Python, or Perl scripting.
• Strong understanding of advanced-node challenges, low-power design, UPF, power gating, multi-Vt, voltage scaling, STA, and LEC.
• Eligibility to access U.S. export-controlled technology is required; employment may depend on citizenship, permanent residency, or prior license approval.

Culture & Benefits

• Collaborative environment focused on curiosity and solving difficult technical problems.
• Competitive compensation package and benefits.
• Opportunity to influence customer commitments through PPA and schedule results.
• Exposure to hardening and delivering RISC-V CPU and AI accelerator IP on advanced process nodes.
• Equal opportunity employment.