DFT Intern (ASIC)

Location: On-site at the San Jose, CA office

Company

hirify.global develops inference-focused AI hardware by co-designing chips, racks, software, and manufacturing systems.

What you will do

• Review and refine DFT flow automation for chip-level regression on Caelius.
• Contribute to DFT verification for MBIST, Scan, BSCAN, and SSN simulations.
• Develop flows for multiple ATPG fault models.
• Work across frontend and backend design teams on ASIC development.
• Learn about transformers and modern AI hardware systems.

Requirements

• Progress toward a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with Verilog or SystemVerilog and digital logic design fundamentals.
• Exposure to ASIC or SoC design concepts and standard ASIC flow steps, including synthesis, STA, and DFT.
• Familiarity with scripting in Python, Tcl, or another language.
• Ability to learn quickly in a fast-paced, high-autonomy environment.

Nice to have

• Knowledge of MBIST, scan insertion, scan compression, clocking, and reset schemes.
• Experience with Tessent or similar DFT tooling.
• Familiarity with ATPG fault models such as SAF, TDF, BDF, IDDQ, and PDF.
• Exposure to DFT flow automation or regression infrastructure.

Culture & Benefits

• 12-week paid internship program.
• Housing support for interns who relocate.
• Daily lunch and dinner at the office.
• Direct mentorship from experienced engineers and technical leaders.
• Fully in-person collaboration in San Jose, with engineering and research work across disciplines.