2 дня назад
Senior Staff Digital Design Engineer (RAIN RFID)
158 700 - 238 100$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Staff Digital Design Engineer (RAIN RFID): Designing next-generation digital subsystems for RAIN RFID reader integrated circuits across architecture, RTL, tapeout, silicon bring-up, and validation with an accent on mixed-signal architectures, control loops, calibration engines, and ASIC/SoC methodologies. Focus on defining micro-architectures, closing timing, implementing DFT strategies, debugging silicon behavior, and leading multidisciplinary engineering workstreams.
Location: Remote within the United States
Salary: $158,700–$238,100 USD per year, plus potential merit increases, annual bonuses, and stock awards.
Company
provides an AI-powered matching and application-review platform connecting candidates with hiring companies.
What you will do
- Lead digital design for RAIN RFID reader ICs from architecture and micro-architecture through RTL, tapeout, and post-silicon validation.
- Develop executable models and RTL for complex digital and mixed-signal subsystems.
- Define mixed-signal architectures with chip architects and RF/analog engineers, including control loops, calibration engines, and analog IP interfaces.
- Collaborate with verification and physical design teams on functionality, timing closure, signal integrity, and production-ready silicon.
- Define DFT strategies including scan insertion, BIST, boundary scan, MBIST, and ATPG.
- Improve ASIC/SoC design flows and methodologies while mentoring engineers and supporting silicon bring-up and debugging.
Requirements
- Bachelor’s degree in Computer Engineering or a related technical field with 12+ years of relevant experience, or an equivalent master’s or PhD pathway.
- 12+ years of hands-on RTL design experience and at least 2–3 complete tapeout cycles, preferably with mixed-signal or RF-integrated ICs.
- Strong expertise in digital logic design, micro-architecture, synthesis, timing closure, CDC analysis, clock gating, low-power methodologies, and static timing analysis.
- Advanced Verilog and SystemVerilog skills, plus experience with UVM, functional coverage, assertion-based verification, and DFT methodologies.
- Scripting experience with Python, Perl, UNIX shell, or similar automation tools.
- Ability to lead complex technical initiatives, mentor engineers, and collaborate across digital, analog, RF, physical design, CAD/EDA, and systems engineering.
Culture & Benefits
- Remote-eligible work arrangement for U.S.-based employees.
- Base salary with eligibility for merit increases, annual bonuses, and stock awards.
- 401(k) plan with company matching and comprehensive healthcare benefits for U.S.-based employees.
- Open PTO policy supporting work-life balance.
- Opportunities to influence engineering methodologies, mentor engineers, and contribute to advanced semiconductor technology.
- Innovation-focused, collaborative, inclusive workplace with equal-opportunity commitments and reasonable accommodations.
Hiring process
- uses an AI-powered matching process to evaluate applications against the role’s core requirements.
- Shortlisted candidates are shared with the hiring company, whose internal team manages interviews, assessments, and subsequent steps.
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