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6 часов назад

Design For Testability (DFT) Engineer (ASIC)

150 000 - 275 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Релокация
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Design For Testability (DFT) Engineer (ASIC) (ASIC/SoC): Developing and validating DFT architectures for high-performance inference chips with an accent on scan insertion, boundary scan, BIST, MBIST, and production test patterns. Focus on silicon bring-up, failure analysis, ATE optimization, yield improvement, and reliable high-volume manufacturing.

Location: On-site in San Jose, California

Salary: $150,000–$275,000 per year plus equity

Company

hirify.global builds chips, racks, software, and manufacturing systems for high-throughput, low-latency frontier AI inference.

What you will do

  • Develop DFT architectures for ASIC and SoC designs to improve test coverage, debugging, and fault isolation.
  • Integrate scan insertion, boundary scan, BIST, and MBIST methodologies.
  • Create DFT verification plans and apply simulation-based and formal verification techniques.
  • Analyze test results and silicon debug data to improve coverage, yield, reliability, and product quality.
  • Support silicon bring-up, post-silicon validation, failure analysis, and ATE program development for volume production.
  • Document DFT architectures and procedures while sharing best practices through training and mentorship.

Requirements

  • 10+ years of DFT engineering experience with ASIC or SoC products.
  • Strong knowledge of digital design, verification, and DFT implementation practices.
  • Proficiency in SystemVerilog and industry-standard EDA tools such as Synopsys DFT Compiler, Cadence Encounter Test, or Mentor Tessent.
  • Scripting and automation experience with Python, Perl, or TCL.
  • Experience leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments.
  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; a Master’s degree is preferred.

Nice to have

  • Mixed-signal DFT and analog testability integration experience.
  • Experience with IEEE 1149.1, IEEE 1500, yield analysis, product engineering, or test cost reduction.

Culture & Benefits

  • Fully in-person work in San Jose, with collaboration across engineering and research disciplines.
  • Medical, dental, and vision coverage, plus a $500 monthly credit for waiving medical benefits.
  • $2,000 monthly housing subsidy for employees living within walking distance of the office.
  • Relocation support for moves to San Jose.
  • Wellness benefits, daily office lunch and dinner, and an unlimited compute budget subject to ROI justification.

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