Senior Microarchitect (AI)

Location: Santa Clara County, CA; San Francisco, CA; Houston, TX; Mountain View, CA; Santa Clara, CA; San Francisco Bay Area; Berkeley, CA; Munich, Bavaria, Germany; or Remote (U.S.)

Salary: $300,000–$350,000

Company

hirify.global is partnered with a well-funded, venture-backed startup developing AI infrastructure and chip-level systems for more efficient inference workloads.

What you will do

• Design execution pipelines, scheduling and control logic for AI compute hardware.
• Define datapaths, register files, scratchpads and local memory hierarchies.
• Implement support for FP16, BF16, FP8 and FP4 numeric formats.
• Optimize compute throughput, utilization, power, area and memory bandwidth within SoC constraints.
• Collaborate with architecture, compiler, kernel and performance teams to evaluate AI workloads, ISA and programming-model trade-offs.
• Lead RTL implementation and support verification, timing closure, emulation, debug, bring-up and post-silicon performance tuning.

Requirements

• Strong background in AI compute or accelerator design, including complex multi-block units across multiple generations of process technology.
• Deep understanding of matrix and vector pipelines, floating-point numerics, quantization and performance-per-watt optimization.
• Experience delivering real silicon.
• Master’s degree or PhD and 5+ years of experience.
• For remote work, candidates must be based in the U.S.

Nice to have

• Experience with startup or early-stage silicon programs.

Culture & Benefits

• Opportunity to take substantial ownership in building new AI infrastructure from the ground up.
• Work on chip- and system-level technology targeting major improvements in inference performance and efficiency.
• Collaboration across architecture, compiler, kernel, performance, verification and silicon teams.