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3 дня назад

Senior Design Verification Engineer (AI)

180 000 - 350 000$
Формат работы
remote (только USA)/hybrid/onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Germany
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior Design Verification Engineer (AI): Owning verification for complex IP, subsystems, and full-chip functionality for a next-generation AI accelerator with an accent on UVM-based environments and scalable testbench architecture. Focus on driving functional closure, debugging complex design issues, and implementing AI-assisted verification workflows to ensure first-pass silicon success.

Location: Hybrid or On-site in San Francisco Bay Area, Houston, TX, or Remote (U.S.); also includes Munich, Germany.

Salary: $180,000–$350,000 per year.

Company

hirify.global is partnering with a well-funded, early-stage AI hardware startup building a complete hardware/software stack for next-generation AI inference platforms.

What you will do

  • Own verification for a major functional area of a cutting-edge AI accelerator.
  • Define and execute comprehensive verification strategies across IP, subsystem, SoC, and emulation environments.
  • Develop reusable UVM-based verification environments, test plans, and coverage models.
  • Build and enhance AI-assisted verification workflows to improve productivity.
  • Drive functional closure by debugging complex design issues in collaboration with architecture and design teams.

Requirements

  • 5+ years of hands-on pre-silicon verification experience on complex ASIC or SoC programs.
  • Deep understanding of UVM methodology, constrained-random verification, and scalable testbench architecture.
  • Strong experience in block/subsystem verification, CPU integration, or hardware emulation.
  • Ability to interpret hardware and software specifications into effective verification strategies.
  • Experience setting priorities and delivering against aggressive development schedules.

Nice to have

  • Experience with RISC-V architectures.
  • Knowledge of formal verification methodologies.
  • Familiarity with hardware emulation platforms like Cadence Palladium or Siemens Veloce.
  • Post-silicon validation or bring-up experience.

Culture & Benefits

  • Meaningful equity participation in an early-stage startup.
  • Comprehensive medical, dental, and vision coverage.
  • 401(k) retirement plan.
  • Generous paid time off.

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