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4 дня назад

MTS - Compiler Engineer (AI Hardware)

180 000 - 320 000$
Формат работы
remote (только USA)/onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
MTS - Compiler Engineer (AI Hardware) (LLVM/custom accelerator backend): Develop and optimize compiler infrastructure that maps software onto a custom accelerator architecture with an accent on instruction selection, register allocation, scheduling, code generation, and binary tooling. Focus on compiler-hardware co-design, debugging correctness and performance regressions, and supporting architecture bring-up through simulation, emulation, or pre-silicon environments.

Location: Mountain View, California; remote within the United States. Other listed locations include San Francisco, Santa Clara, Berkeley, and Houston, California/Texas.

Salary: $180,000–$320,000 per year

Company

hirify.global is recruiting for an early-stage AI hardware company developing custom accelerator technology.

What you will do

  • Develop and maintain a compiler backend for a custom accelerator instruction set.
  • Implement instruction selection, register allocation, scheduling, lowering, and code generation.
  • Build target descriptions, machine models, assembler, linker, loader, and binary-format support.
  • Debug correctness issues and performance regressions across the compilation flow.
  • Improve generated-code quality, throughput, latency, and hardware utilization.
  • Collaborate with architecture, chip design, runtime, frontend, middle-end, kernel, and systems engineers on hardware-software co-design and platform bring-up.

Requirements

  • 5+ years of compiler engineering experience.
  • Hands-on experience developing or extending an LLVM target backend, including TableGen, Machine IR, target lowering, instruction selection, register allocation, scheduling, and code emission.
  • Strong knowledge of computer architecture and instruction-set design.
  • Experience with scalar, vector, floating-point, or accelerator execution pipelines.
  • Strong C++ programming skills and the ability to debug compiler correctness and performance issues.
  • Must work from the United States for the remote arrangement.

Nice to have

  • Experience with custom ISA or new-target bring-up.
  • MLIR or other intermediate-representation frameworks.
  • GPU, NPU, DSP, accelerator, RISC-V, ARM, or x86 compiler experience.
  • Runtime or driver integration, architectural simulators, emulators, or pre-silicon environments.
  • Compiler optimization for AI or high-performance computing workloads.

Culture & Benefits

  • Early-stage environment with direct influence over compiler and hardware development.
  • Close collaboration across compiler, architecture, hardware, runtime, and systems disciplines.
  • Work spans early architecture development through production deployment.

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