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4 часа назад

Top-Level Physical Design Engineer (AI)

200 000 - 300 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Релокация
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Top-Level Physical Design Engineer (AI/ASIC): Own full-chip implementation for frontier AI inference hardware from synthesis through GDSII completion with an accent on clocking, timing closure, physical verification, and PPA optimization. Focus on debugging complex physical verification violations, driving ECO closure, building tapeout-ready methodologies, and achieving final signoff on advanced process nodes.

Location: On-site in San Jose, Santana Row. Relocation support is available for candidates moving to San Jose.

Salary: $200,000–$300,000 per year plus significant equity

Company

hirify.global develops AI hardware, chips, racks, software, and manufacturing systems for high-throughput, low-latency frontier inference clusters.

What you will do

  • Own full-chip physical implementation from synthesis through GDSII completion, including floorplanning, placement and routing, clocking, timing analysis, physical verification, and sign-off.
  • Manage full-chip clocking across all PVT corners and modes and drive MMMC timing closure.
  • Define timing constraints and hierarchical timing budgets between the top level and blocks.
  • Drive functional and timing ECO closure and achieve final timing sign-off for tapeout.
  • Own physical verification closure across block, subsystem, and full-chip levels, covering DRC, LVS, ERC, antenna, density, fill, and top-level integration.
  • Debug and fix complex layout and routing violations in Innovus while building a repeatable, tapeout-ready verification methodology.

Requirements

  • 10+ years of experience with chip planning, top-level physical design, and floorplanning.
  • Experience with top-level and full-chip closure on advanced process nodes, including 5nm and below.
  • Experience with Cadence Innovus and Genus or Synopsys Fusion Compiler RTL-to-GDSII flows.
  • Experience with Synopsys PrimeTime and Cadence Tempus for timing sign-off.
  • Experience with Pegasus or Calibre for physical verification sign-off.
  • Experience with hierarchical timing budgeting, constraint management, ECO closure, top-level assembly, routing, and layout fixes.

Nice to have

  • Familiarity with modern ML and LLM model architectures.
  • Python or another scripting language.
  • Experience with AI tools for programming and coding.
  • Startup experience or comfort working in fast-paced environments.

Culture & Benefits

  • Fully in-person work with collaboration across engineering and research disciplines.
  • Medical, dental, and vision coverage, plus a $500 monthly credit for waiving medical benefits.
  • $2,000 monthly housing subsidy for employees living within walking distance of the office.
  • Relocation support for moving to San Jose.
  • Wellness benefits, daily office lunch and dinner, and an unlimited compute budget subject to ROI justification.

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