Senior EDA Tools Software Engineer (EDA)

Location: Santa Clara, California, United States. Hybrid work model with time split between the assigned hirify.global site and off-site work.

Annual salary: $173,660–$330,340 USD.

Company

hirify.global develops semiconductor and computing technologies across areas including AI, analytics, and cloud-to-edge systems.

What you will do

• Architect, design, and implement a scalable chassis automation tool for multiple SoC programs.
• Translate architecture specifications and high-level requirements into topology, parameters, RTL, register definitions, timing, integration, and verification collateral.
• Develop schema-driven automation and code-generation flows for configurable interconnect and chassis components.
• Integrate frontend and backend tool flows to validate generated RTL, Verilog, SDC, RDL, and related artifacts.
• Build automation and analysis capabilities for Power, Performance, and Area optimization loops.
• Lead delivery across architecture, RTL, verification, and SoC integration teams while mentoring engineers.

Requirements

• Bachelor’s degree with 7+ years of relevant experience, or master’s degree with 6+ years, in CAD/EDA tooling, design automation, semiconductor development, electrical engineering, computer science, or a related field.
• 5+ years of experience building scalable and maintainable software systems or frameworks.
• 4+ years of experience with Python or a similar language and structured schemas such as JSON or YAML.
• 2+ years of experience with templating systems or code-generation frameworks for RTL or design collateral.
• 1+ year of experience with Git, code reviews, unit and integration testing, and CI/CD.
• Ability to interpret architecture or microarchitecture specifications and convert them into robust software implementations.

Nice to have

• EDA tooling, digital SoC design, RTL hierarchy, synthesis flows, or parameterized IP design experience.
• SystemVerilog experience for understanding and validating generated design outputs.
• Experience with NoC architectures or AXI, CHI, PCIe, UCIe, or similar interconnect protocols.
• Knowledge of IP-XACT, graph-based algorithms, topology generation, connectivity modeling, or routing problems.
• Experience with GUI development or semiconductor product development environments.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Health, retirement, vacation, stock bonuses, and other total compensation benefits.
• Hands-on technical leadership with cross-functional collaboration and broad organizational impact.
• AI-assisted workflows are part of everyday development.