Senior Staff Engineer Digital IC Build Flow and Methodology (Semiconductors)

TL;DR

Senior Staff Engineer Digital IC Build Flow and Methodology (Semiconductors): Architecting, implementing, and maintaining scalable build scripts and front-end methodology for complex digital IC designs with an accent on compilation, simulation, and regression flow optimization. Focus on enhancing build performance through dependency analysis, developing CI/pre-submit verification flows, and integrating industry EDA toolchains.

Location: Westborough, MA, Austin, TX, or Santa Clara, CA. Applicants must be eligible to access export-controlled information as defined under U.S. export control laws (EAR).

Salary: $151,000 - $223,440 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Design and maintain chip design build flows for block, subsystem, and full-chip simulations.
• Develop build scripts and orchestration logic for compile, elaborate, and regression workflows.
• Optimize build performance using dependency analysis, caching, and incremental builds.
• Define and evolve methodology standards for front-end design and verification.
• Architect CI and pre-submit verification flows to reduce turnaround time and improve quality.
• Collaborate with RTL and DV teams to debug complex infrastructure and build-system issues.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• 8+ years of experience in ASIC/SoC design, verification, or methodology roles.
• Proficiency in Python and at least one of TCL, C/C++, or shell scripting.
• Experience with make-based or graph-based build systems.
• Deep understanding of front-end chip design flows and EDA toolchains.
• Strong problem-solving skills and experience debugging large-scale infrastructure.

Nice to have

• Experience with Bazel or similar dependency-graph build systems.
• Knowledge of CI systems like Jenkins and compute-farm environments.
• Experience with multi-chip or chiplet-based designs.
• Experience mentoring junior engineers.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards for milestones and contributions.