Principal Digital Design Engineer (AI Infrastructure)

Location: San Jose, California, United States

Salary: $185,000–$230,000 USD per year

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

• Define micro-architectures and develop complex digital blocks and subsystems for high-performance connectivity products.
• Drive RTL implementation, functional simulation, synthesis, and block-level ownership through GDS.
• Collaborate with verification teams on test plans, coverage closure, and complex issue debugging.
• Lead timing-closure activities and implement Design-for-Test features.
• Support post-silicon bring-up, debug, and failure analysis while driving designs to production.
• Mentor junior engineers and improve silicon development processes.

Requirements

• Bachelor’s degree in electrical engineering or equivalent and 8+ years of hands-on experience developing complex SoC or silicon products.
• Experience in server, storage, and/or networking markets and with advanced CMOS nodes of 7 nm or smaller.
• Deep expertise in at least one high-speed protocol, such as PCIe, Ethernet, InfiniBand, or DDR.
• Experience with timing closure, gate-level simulation, DFT implementation, third-party IP integration, and verification.
• Proficiency with Cadence and/or Synopsys digital design flows and familiarity with UVM-based verification.
• Strong cross-functional communication, collaboration, prioritization, and independent problem-solving skills.

Nice to have

• Experience delivering multiple high-performance designs to production in data-center environments.
• Collaboration with embedded firmware teams and understanding of firmware development constraints.
• Familiarity with embedded processor subsystems such as RISC-V or Arm.
• Contributions to design methodology, CAD automation, or design infrastructure.

Culture & Benefits

• Collaborative work with verification, physical design, DFT, post-silicon, and firmware teams.
• Opportunity to contribute to AI infrastructure and next-generation connectivity products.
• Inclusive environment encouraging applications from people with diverse backgrounds and experiences.