Senior DFT Logic Design Engineer (ASIC)

Location: Hybrid work model in the United States, with primary location in Phoenix, Arizona, and additional locations in Santa Clara, California, and Hillsboro, Oregon. US citizenship is required.

Salary: $141,910–$269,100 USD annual salary

Company

hirify.global Foundry delivers advanced semiconductor process, packaging, IP, and silicon design services for AI, aerospace, defense, government, and other demanding applications.

What you will do

• Support hirify.global Foundry customers with PDKs, DFT/DFM insertion, ATPG validation methodologies, and design flows.
• Collaborate with internal engineering teams, customer design teams, IP providers, and EDA vendors to resolve implementation issues.
• Drive DFT/DFM and ATPG validation methodologies, capabilities, flows, and documentation at block and SoC levels.
• Support customer design challenges and tape-outs through tool, flow, and methodology guidance.
• Create technical content and application notes, and deliver training and presentations.

Requirements

• US citizenship and the ability to obtain a US Government Security Clearance are required.
• Bachelor’s degree in Electrical or Computer Engineering, Computer Science, or another STEM-related field.
• At least 3 years of experience with advanced CMOS processes at 16 nm or below.
• At least 3 years of experience implementing ASIC DFT/DFM insertion, including MBIST, LBIST, SCAN, and JTAG, at block and full-chip levels.
• Experience with ATPG validation, DFT timing, and DFT signoff at SoC level.
• At least 4 years of experience with Python, Perl, Tcl, and/or shell scripting.

Nice to have

• Active US Government Security Clearance at Secret level or higher.
• Postgraduate STEM degree and semiconductor foundry experience.
• Experience with EDA tools for MBIST, hierarchical SCAN and JTAG insertion, DFT constraint generation, and ATPG validation.
• Experience developing DFT/DFX insertion and ATPG validation flows, and collaborating with RTL, hard IP, and physical design engineers.
• Customer-facing experience and experience providing technical direction to engineering teams.

Culture & Benefits

• Hybrid work model combining on-site work at an assigned hirify.global site with off-site work.
• Competitive compensation, stock bonuses, health benefits, retirement benefits, and vacation.
• Access to advanced foundry technologies and comprehensive EDA tool suites.
• Professional development in DFT methodologies and foundry services.
• Opportunity to contribute to aerospace, defense, government, and national-security semiconductor applications.