I/O Design Engineer (AI)

Location: Chandler, Arizona, USA

Annual base salary: USD 109,700–175,500

Company

hirify.global develops semiconductor technologies and advanced integrated-circuit solutions, including AI-focused programs.

What you will do

• Design CMOS I/O, bandgap references, op-amps, comparators, and power-on-reset circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter, and power.
• Perform transistor reliability and EMIR analysis.
• Collaborate with layout teams on physical design and verification.
• Build Verilog, Synopsys Liberty, and IBIS models and maintain technical documentation.
• Support chip-level integration and silicon bring-up in test chips and customer products.

Requirements

• MS or PhD in Electrical Engineering.
• 6+ years of I/O or analog circuit design experience.
• Deep proficiency with Cadence Virtuoso schematic/layout capture and SPICE/Spectre circuit simulation.
• Strong knowledge of GPIO, I2C, I3C, eMMC, RGMII, and SPMI protocols.
• Familiarity with ESD, latch-up, EMI, and signal integrity.
• Experience with advanced CMOS FinFET and GAA process nodes, including technology limitations and PPA tradeoffs.

Culture & Benefits

• Collaborative engineering environment with opportunities for growth and development.
• Discretionary annual bonus and new-hire and annual equity awards.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and ESPP.
• Paid holidays, sick leave, vacation, and applicable family and other leave programs.