I/O Design Engineer (AI)

Location: Chandler, Arizona, United States

Salary: USD 109,700–175,500 annual base salary, plus discretionary bonus and equity awards.

Company

hirify.global's Central Engineering Group develops semiconductor IP and advanced technologies for customer products and AI programs.

What you will do

• Design CMOS I/O, bandgap references, op-amps, comparators, and power-on-reset circuits.
• Run AC/DC, signal integrity, jitter, and power simulations.
• Perform transistor reliability and EMIR analysis.
• Collaborate with layout teams on physical design and verification.
• Build Verilog, Synopsys Liberty, and IBIS models and maintain technical documentation.
• Support chip-level integration and silicon bring-up for test chips and customer products.

Requirements

• MS or PhD in Electrical Engineering.
• 6+ years of I/O or analog circuit design experience.
• Proficiency with Cadence Virtuoso schematic and layout capture and SPICE/Spectre simulation.
• Knowledge of GPIO, I2C, I3C, eMMC, RGMII, and SPMI protocols.
• Experience with ESD, latch-up, EMI, and signal integrity.
• Experience with advanced CMOS FinFET and GAA process nodes, including technology limitations and PPA tradeoffs.

Culture & Benefits

• Collaborative engineering environment with growth and development opportunities.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, paid holidays, paid sick leave, and vacation time.
• Discretionary annual bonus and new-hire and annual equity awards.