IP Logic Design Engineer (3D NAND)

Location: San Jose, CA, United States

Salary: USD 105,440–164,800 per year

Company

hirify.global is a multibillion-dollar memory technology company developing 3D NAND products and data storage solutions with operations across the United States, Asia, Europe, and the Americas.

What you will do

• Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components.
• Define microarchitecture specifications, implement SystemVerilog RTL, generate synthesis netlists, apply timing constraints, perform static timing analysis, resolve violations, and drive design sign-off.
• Develop and optimize microcode-based read, program, erase, and power-on algorithms using proprietary instruction sets and compilers.
• Contribute to next-generation 3D NAND architecture to improve density, die size, performance, power, and cost.
• Build unit-level verification environments, run RTL and gate-level simulation regressions, and ensure functional and code coverage.
• Support analog and mixed-signal simulation reviews, post-silicon debug, failure analysis, power and performance modeling, and DFT development.

Requirements

• MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience.
• Expertise in Verilog and SystemVerilog and a deep understanding of ASIC design flows, including RTL design, logic synthesis, STA, and ECOs.
• Experience with lint tools, CDC/RDC analysis, timing constraints, design verification tools, and automation scripting.
• Ability to work independently across pre-silicon and post-silicon debug cycles.

Nice to have

• Experience with 3D NAND flash memory logic design.

Culture & Benefits

• Full-time position within the NAND Development department.
• Work in a diverse, inclusive, collaborative, results-driven, and team-oriented environment.
• Contribute to memory technologies and optimized data storage products.