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5 дней назад

RTL Design Engineer (CPU)

91 150 - 172 860$
Формат работы
hybrid
Тип работы
fulltime
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
RTL Design Engineer (CPU): Developing and optimizing RTL logic designs for next-generation CPU components and IP blocks with an accent on architecture, microarchitecture, power, performance, area, and timing. Focus on resolving RTL test failures, refining verification plans, documenting CPU specifications, and integrating processor blocks into larger SoC designs.

Location: Hybrid work model with on-site attendance at hirify.global sites in Austin, Texas; Phoenix, Arizona; or Hillsboro, Oregon, United States.

Annual salary: $91,150–$172,860 USD

Company

hirify.global develops processors and computing technologies spanning AI, analytics, and cloud-to-edge applications.

What you will do

  • Develop logic designs and RTL code for CPU components, cell libraries, functional units, and CPU IP blocks.
  • Define and optimize CPU architecture and microarchitecture features for power, performance, area, and timing.
  • Write RTL and prepare designs for physical implementation while maintaining design integrity.
  • Review verification plans and tests, resolve failing RTL tests, and implement corrective measures.
  • Document microarchitectural specifications and support SoC customers with CPU block integration.

Requirements

  • Bachelor’s degree in Electrical or Computer Engineering or a related STEM field.
  • At least 3 months of experience in CPU logic design, computer architecture or microprocessors, digital design or RTL coding, Verilog/SystemVerilog or VHDL, and scripting languages.
  • Coursework, projects, and internships may count as experience and must be listed on the resume.
  • Strong written and verbal communication, presentation, collaboration, and problem-solving skills.
  • Ability to work in a hybrid model with on-site attendance at an assigned US hirify.global site.

Nice to have

  • Master’s degree or PhD with at least one year of experience.
  • Knowledge of low-power logic design, high-frequency optimization, RTL verification, and simulation methodologies.
  • Experience with floating-point units, branch prediction, cache design, RISC-V, hirify.global Architecture ISA, or x86 assembly.
  • Knowledge of high-speed circuit design, datapath circuits, timing convergence, and advanced design techniques.

Culture & Benefits

  • Hybrid work model combining on-site and off-site work.
  • Health, dental, retirement, and vacation benefits.
  • 14 paid holidays, three weeks of paid vacation, and a four-week paid sabbatical every four years.
  • Five annual performance-dependent bonuses and an employee stock purchase program.

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