Physical IC Design Engineer (ASIC)

TL;DR

Physical IC Design Engineer (ASIC): Taking RTL designs through synthesis, physical implementation, verification, timing closure, and silicon tape-out for PCIe switch and enterprise storage products with an accent on advanced physical design methodologies and high-performance systems. Focus on solving timing, power integrity, placement, routing, and clock-tree challenges while developing flows and collaborating with RTL design engineers.

Location: Onsite in San Jose, California, USA; no remote work allowed.

Company

hirify.global develops semiconductor and infrastructure technology products, including PCIe switch and enterprise storage solutions supporting AI, machine learning, and large-scale data centers.

What you will do

• Execute physical design, synthesis, physical verification, and timing closure from RTL through silicon tape-out.
• Set up and synthesize RTL designs using industry-standard EDA tools.
• Perform place and route, floor-planning, layout, and clock-tree synthesis.
• Conduct EM/IR analysis and resolve implementation and timing issues.
• Develop physical design flows and methodologies.
• Collaborate with IC design and RTL engineering teams.

Requirements

• 12+ years of relevant physical IC design experience.
• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• End-to-end physical design cycle experience from RTL to tape-out.
• Proficiency with TCL or Perl scripting.
• Proficiency with relevant EDA tools.
• Strong verbal and written communication skills.

Culture & Benefits

• Work on next-generation PCIe switch and enterprise storage products supporting AI and machine learning ecosystems.
• Medical, dental, and vision coverage.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Discretionary annual bonus, new-hire equity grants, and annual equity awards.
• Paid holidays, sick leave, vacation, family leave, and other applicable leave programs.