Physical IC Design Engineer (AI/ML)

Location: San Jose, California, USA; onsite only with no remote work

Company

hirify.global develops PCIe switch products supporting AI and Machine Learning ecosystems and enterprise storage products for large-scale datacenters.

What you will do

• Execute physical design, synthesis, physical verification, and timing closure from RTL to silicon tape-out.
• Set up and synthesize RTL while applying timing-closure methods and strategies.
• Perform EM/IR analysis, place and route, clock tree synthesis, floor-planning, and layout.
• Develop physical design flows and methodologies.
• Collaborate with IC Design RTL Engineers.

Requirements

• 12+ years of relevant physical IC design experience.
• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• Experience with the full physical design cycle from RTL to tape-out.
• Proficiency with related EDA tools.
• TCL and Perl scripting skills.
• Excellent verbal and written communication skills.

Culture & Benefits

• Discretionary annual bonus opportunity.
• Competitive new-hire equity grant and potential annual equity awards.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation time, and applicable family and other leave programs.