Principal Digital Design Engineer (PCIe)

Location: San Jose, California, United States. Authorized to work in the US and start immediately.

Base salary: $185,000–$230,000 USD annually, depending on location, experience, and internal pay equity.

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions based on CXL, Ethernet, NVLink, PCIe, and UALink technologies, supported by its COSMOS software suite.

What you will do

• Develop micro-architecture and front-end circuit designs for high-performance network controllers.
• Implement RTL, synthesis, IP integration, simulations, timing closure, GLS, and DFT flows.
• Own complex SoC and silicon designs from architecture through GDS and production.
• Work with PCIe, UALink, Esun, Ethernet, and other high-speed communication protocols.
• Drive block-level verification, silicon bring-up, and debug activities.
• Support customer meetings while prioritizing multiple technical projects with minimal supervision.

Requirements

• Bachelor’s degree in Electrical Engineering; a Master’s degree is preferred.
• 8+ years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
• Thorough hands-on knowledge of PCIe, UALink, Esun, Ethernet, or comparable high-speed protocols.
• Front-end design expertise covering architecture, RTL, simulation, synthesis, timing closure, GLS, DFT, and scan test insertion.
• Experience with Synopsys or Cadence digital design tools and flows, UVM-based verification, silicon bring-up, and small-geometry CMOS at 28nm or below.
• US work authorization and immediate availability are required.

Nice to have

• Firmware development in C and scripting in Python or equivalent languages.
• Experience developing or supporting PCIe or Ethernet switch products.

Culture & Benefits

• Work in an environment focused on creativity, innovation, and diverse perspectives.
• Collaborate with hyperscalers and ecosystem partners on AI infrastructure solutions.
• Contribute to customer-focused connectivity architectures for scale-up and scale-out systems.