Principal Physical Design Engineer (AI Infrastructure)

Location: San Jose, California, United States

Salary: $185,000–$240,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may be available.

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

• Own the end-to-end RTL2GDS flow across synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff on advanced process nodes.
• Drive block- and chip-level place-and-route strategy, congestion resolution, routing convergence, and high-frequency design implementation.
• Lead timing, power, physical verification, reliability, and multi-mode multi-corner signoff, including STA, UPF/CPF, IR/EM, LVS, DRC, antenna, and ERC closure.
• Lead tapeout execution, including final ECO closure, GDS handoff, and post-tapeout support through fabrication.
• Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams on floorplanning, clocking, and power delivery strategies.
• Establish physical design methodology, develop automation flows, mentor engineers, and represent Physical Design in program-level technical decisions.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of physical design experience with multiple tapeouts on advanced process nodes, including 7nm or below.
• Deep expertise in synthesis, place and route, clock tree synthesis, and timing closure using tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, or Cadence Innovus.
• Strong command of low-power design techniques, including multi-Vt, power gating, DVFS, and UPF.
• Proficiency in Tcl and Python scripting for flow automation.
• Proven experience delivering high-frequency, high-complexity SoC blocks or full-chip implementations to production.

Nice to have

• Master’s degree in Electrical Engineering or Computer Engineering.
• Experience with high-speed SerDes designs, PCIe Gen 6/7, or UALink/UCIe connectivity SoCs.
• Experience with hierarchical implementation and full-chip integration of designs exceeding 500M gates.
• Familiarity with EMIR, thermal analysis, and package co-design.
• Experience mentoring senior engineers and driving methodology adoption across teams.

Culture & Benefits

• Collaborative work across RTL, DFT, analog, package, and CAD disciplines.
• Opportunity to contribute to connectivity silicon powering large-scale AI clusters.
• Inclusive environment that values diverse ideas, backgrounds, and experiences.
• Potential eligibility for discretionary bonus, incentives, and benefits.