physical designasicedatclstatic timing analysissynthesisplace and routephysical verification
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Очень мало
$87к-165к/год
$170к$210кмедиана$250к
По похожим ролям (50) ~ $210к/год
На СНГ рынке: $1.9к/мес ($1.8к - $3к)
68
Средняя вакансия
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Профессиональная роль с четким кругом задач в высокотехнологичном домене. Однако сервисный характер компании и широкий диапазон зарплаты могут повлиять на стабильность и предсказуемость дохода.
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Сервисная компанияДиапазон зарплатыСовременный стекПонятные задачи
Оценка от Hirify AI
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Physical Design Engineer II (IC) (ASIC/EDA): Executing synthesis, place and route, static timing analysis, and physical verification for assigned ASIC partitions with an accent on sub-7nm SoC implementation, low-power design, and signoff convergence. Focus on closing EM/IR and LEC issues, developing TCL-based implementation flows, and troubleshooting EDA methodology problems with design teams and vendors.
Location: Complete on-site in San Jose, California, with travel to Arrow client office locations as requested by client leadership. Listed locations include San Jose, Campbell, and Santa Clara, California, United States.
Salary: Annual hiring range of $87,400–$165,000.
Company
eInfochips, an hirify.global company, provides product engineering and semiconductor design services across multiple industries and global client markets.
What you will do
Execute synthesis, place and route, and static timing analysis for assigned ASIC partitions while meeting schedules and design goals.
Collaborate with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues.
Close electromigration and IR issues and drive logical equivalence checking and physical verification signoff.
Identify physical design challenges early to improve iteration and convergence.
Refine methodologies for synthesis, PnR, EMIR, power delivery networks, and LEC.
Troubleshoot implementation flow issues and work with EDA vendors on resolutions.
Requirements
Bachelor’s degree in electrical engineering, computer engineering, computer science, or a related technical field, or equivalent practical experience.
7+ years of hands-on experience in physical design and implementation, including synthesis, PnR, timing convergence, and physical verification.
Proficiency with EDA tools including Innovus, Tempus, and Quantus, plus a deep understanding of physical design flows and methodologies.
Experience in physical design roles and related activities.
Ability to meet tight schedules and implement low-power design techniques.
Experience with SoC design and implementation.
Expertise in sub-7nm node technologies.
Familiarity with industry-standard EDA tools and their capabilities.
Strong TCL scripting skills for developing custom flows and methodologies with Cadence and Synopsys EDA tools.
Culture & Benefits
Medical, dental, and vision insurance.
401(k) with matching contributions.
Short-term and long-term disability insurance.
Health Savings Account and Health Reimbursement Account options.
Paid sick leave, holidays, and vacation.
Tuition reimbursement and growth opportunities.
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