Static Timing Analysis Design Engineer / Physical Design

Location: Austin (Oakhill, Office), United States of America

Company

hirify.global develops advanced semiconductor products and high-reliability SoCs.

What you will do

• Own end-to-end timing constraint creation, validation, and static timing analysis for complex SoC designs.
• Drive timing correlation and path debugging from synthesis through final timing signoff.
• Collaborate with frontend, IP, DFT, implementation, and full-chip STA teams to resolve timing issues and close designs.
• Develop automated and manual timing ECOs and provide timing feedback throughout the design cycle.
• Support post-silicon bring-up, yield improvement, and production ramp activities.
• Improve scalability, productivity, and design quality through methodology enhancements.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 3–6 years of experience in ASIC or SoC timing analysis.
• Strong knowledge of STA and signoff methodologies and industry timing tools, including Synopsys flows.
• Experience with timing ECO generation, constraints development and validation, and advanced-node implementation at 16nm or below, including 5nm.
• Scripting experience in Python, TCL, and Perl.
• Strong communication and cross-functional collaboration skills.

Nice to have

• Experience with high-reliability SoCs.
• Exposure to AI-driven design methodologies and automation.
• Familiarity with using AI to generate scripts.

Culture & Benefits

• Work on flagship SoCs at advanced technology nodes.
• Directly influence silicon success and product competitiveness.
• Participate in career development and organization-building initiatives.
• Equal employment opportunity and reasonable accommodation are provided in accordance with applicable law.