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22 часа назад

Physical Design Manager (AI)

200 000 - 400 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK/US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Physical Design Manager (AI): Leading end-to-end silicon realization from synthesis and physical floorplanning through timing signoff and GDSII tapeout with an accent on ASIC implementation, PPA optimization, and physical verification. Focus on building the physical design team, closing timing and power-integrity issues, resolving DRC/LVS violations, and executing tapeouts for novel computing architectures.

Location: Hybrid in Silicon Valley, London, or New York City

Salary: $200K–$400K annually, plus equity

Company

hirify.global is an applied AI company building foundational hardware and software for the semiconductor industry, AI infrastructure, and advanced computing systems.

What you will do

  • Lead the physical design team, including hiring, planning, mentoring, and performance feedback.
  • Own the netlist-to-GDSII implementation flow, including floorplanning, power grid design, placement, clock tree synthesis, and place-and-route.
  • Drive timing closure, static timing analysis, power, performance, area, signal integrity, and IR/EM optimization.
  • Collaborate with RTL, architecture, and DFT teams on macro placement, pin assignments, and early physical feasibility.
  • Lead physical signoff activities covering DRC, LVS, ERC, antenna fixes, and foundry handoff.
  • Plan and execute tapeouts, including final stream-out and post-silicon physical debugging.

Requirements

  • At least 3 successful tapeouts led from netlist through signoff, preferably at advanced technology nodes.
  • Deep hands-on experience with physical design tools such as Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, or Calibre.
  • Strong experience resolving STA timing bottlenecks, IR/EM issues, crosstalk, and DRC/LVS violations.
  • At least 7 years of managerial experience in physical design or a related role.
  • Ability to work cross-functionally with RTL, architecture, and DFT teams.
  • Experience with TCL or Python automation for physical design flows.

Nice to have

  • Experience at an AI or high-performance computing chip startup.
  • Experience with custom memory or macro floorplanning, hierarchical top-level implementation, or advanced packaging such as chiplets and 2.5D/3D integration.

Culture & Benefits

  • Cross-functional collaboration across hardware, software, RTL, architecture, and DFT teams.
  • Work on novel computing architectures and advanced silicon systems.
  • Equity is included in the compensation package.
  • Inclusive equal-opportunity workplace with reasonable accessibility accommodations.

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