Назад
Company hidden
5 дней назад

FPGA Design Engineer (Memory Test)

135 400 - 216 600$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
FPGA Design Engineer (Memory Test): Architecting and implementing FPGA solutions for next-generation Flash and DRAM test instrumentation with an accent on digital design, RTL development, timing closure, and laboratory validation. Focus on translating customer requirements into reliable hardware architectures, extending existing FPGA designs, and solving complex high-performance memory testing challenges.

Location: Onsite in San Jose, California, US; occasional travel may be required.

Salary: $135,400–$216,600 base salary, plus potential discretionary bonuses.

Company

hirify.global develops test and automation solutions for manufacturers and advanced technology companies worldwide.

What you will do

  • Architect and implement FPGA solutions for Flash and DRAM test instrumentation.
  • Translate abstract concepts and customer requirements into reliable, extensible, and supportable designs.
  • Develop, maintain, and extend FPGA designs to improve quality and support emerging customer requirements.
  • Perform RTL coding, synthesis, timing closure, simulation, and laboratory validation.
  • Provide technical guidance to junior engineers and collaborate on team-oriented projects.
  • Deliver high-quality products while maintaining schedule commitments.

Requirements

  • Bachelor’s degree or equivalent in Electrical Engineering or a related field with at least 5 years of relevant experience, or a master’s degree with at least 3 years of relevant experience.
  • Experience with digital design and architecture, RTL coding, synthesis, timing closure, and lab validation.
  • Experience performing static timing analysis for ASICs or FPGAs.
  • Experience creating digital simulation testbenches.
  • Experience with C or C++.
  • Familiarity with oscilloscopes, power supplies, waveform generators, and other laboratory equipment.

Nice to have

  • FPGA transceiver-based design experience and familiarity with DRAM and Flash memory interfaces.
  • Experience with Altera or AMD FPGA tool flows and Verilog HDL.
  • Familiarity with UVM methodology, scripting languages, Linux, Windows, and ATE instrumentation.

Culture & Benefits

  • Collaborative, inclusive environment focused on technical excellence and innovation.
  • Medical, dental, vision, and flexible spending account programs.
  • Retirement savings plans, life and disability insurance.
  • Paid vacation and holidays, tuition assistance, and additional employee benefits.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →