Principal Product Engineer (IP Design)

TL;DR

Principal Product Engineer (IP Design): Leading the integration and validation of PHY and controller SoC IPs with an accent on RTL simulation, gate-level verification, and technical support. Focus on resolving complex subsystem implementation problems and optimizing product roadmaps through customer feedback.

Location: Shanghai (Onsite)

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware tools.

What you will do

• Act as the primary technical interface to resolve complex subsystem application and implementation issues.
• Support Pre-Silicon integration, post-silicon bring-up, and verification of PHY and controller SoC integration.
• Perform RTL and gate-level simulations to ensure functionality and assist with timing closure.
• Engage with customers to identify critical technical problems and manage escalations.
• Develop comprehensive knowledge bases and provide feedback to internal R&D teams for product improvement.
• Create and deliver technical training, seminars, and documentation to support customer success.

Requirements

• 8+ years of experience in verification and design, specifically with IP development.
• Strong background in digital electronics, Verilog, SystemVerilog, and UVM methodology.
• Practical knowledge of memory or communication interface protocols (MIPI, PCIe, DDR, LPDDR, HBM, or USB).
• Proficiency in scripting languages such as TCL, Perl, or Python.
• Bachelor’s or Master’s degree in Electronics or Electrical Engineering.
• Fluent spoken English

Nice to have

• Experience with hirify.global-specific tools, EDA workflows, or similar IP design platforms.

Culture & Benefits

• Opportunity to work as a leader and innovator in the technology sector.
• Collaborative environment working across global, cross-functional teams.
• Focus on solving high-impact technical challenges.