IC Design Engineer (DFT)

TL;DR

IC Design Engineer (DFT) (ASIC): Developing state-of-the-art IC solutions using CMOS cell-based ASIC technologies with an accent on DFT architecture, test insertion, and timing verification. Focus on implementing scan, MBIST, and Logic BIST for 5nm/3nm designs, and debugging DFT patterns on ATE.

Location: Onsite in Shanghai, China (Zhangjiang Hi Tech)

Company

hirify.global is a leading global semiconductor company providing advanced connectivity and infrastructure solutions.

What you will do

• Define chip-level DFT architecture.
• Implement DFT schemes including scan, boundary scan, MBIST, Logic BIST, and SSN.
• Verify all DFT logic and test patterns through simulation.
• Perform static timing analysis (STA) for test modes.
• Collaborate on ATE bring-up and debug DFT patterns on ATE.

Requirements

• Bachelor or Master degree in Microelectronics or a related discipline.
• 5+ years of related professional experience required.
• Deep understanding of DFT methodology (BIST, SCAN, JTAG, ATPG).
• Proficiency with Mentor and Synopsys DFT tools.
• Experience developing constraints for synthesis and STA.
• Expertise in multi-mode, multi-corner (MMMC) STA and sign-off checks.

Culture & Benefits

• Opportunity to work with cutting-edge 5nm and 3nm design technologies.
• Collaborative team environment focused on personal career growth.
• Equal opportunity employment with a focus on diversity and inclusion.