обновлено 11 дней назад
IC Design Engineer (DFT)
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
IC Design Engineer (DFT) (ASIC/DFT): Developing advanced chip-level DFT architectures and ASIC designs for 5nm/3nm CMOS technologies with an accent on scan, boundary scan, MBIST, Logic BIST, SSN, and test-pattern verification. Focus on implementing and verifying DFT logic, performing multi-mode multi-corner timing analysis, and debugging DFT patterns during ATE bring-up.
Location: Shanghai, Zhangjiang Hi-Tech, China
Company
develops state-of-the-art IC solutions using advanced CMOS cell-based ASIC technologies.
What you will do
- Define chip-level DFT architectures.
- Implement scan, boundary scan, MBIST, Logic BIST, and SSN schemes.
- Verify DFT logic and test patterns through simulation.
- Perform static timing analysis for test modes, including multi-mode and multi-corner analysis.
- Participate in ATE bring-up and debug DFT patterns on automated test equipment.
- Support ASIC development across RTL analysis, synthesis, optimization, timing verification, physical design, vector generation, and post-prototype testing.
Requirements
- Bachelor’s or master’s degree in Microelectronics or a related discipline; an MS degree is preferred.
- 5+ years of relevant IC design or DFT experience.
- Strong understanding of DFT methodologies, including BIST, scan, JTAG, and ATPG.
- Familiarity with Mentor and Synopsys DFT flows and tools.
- Experience developing synthesis and STA constraints.
- Understanding of sign-off checks.
Culture & Benefits
- Full-time opportunity in a collaborative team environment.
- Opportunity to contribute to leading-edge 5nm and 3nm chip designs.
- Career development opportunities through work on advanced IC solutions.
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